Abstract: A receiver particularly suited for an M-BUS is described. During transmission, the receiver is disabled. After each transmission, nodes and states in the receiver are set to prepare the receiver to receive a signal. Once data is sensed, a feedback loop clips the input signal to the receiver to limit the swing of the input signal. The line of the power supply at the lower potential is modulated, rather than modulating the line at the higher potential, for the transmission of data.

Abstract: A hardware interface in an integrated circuit is disclosed. The hardware interface comprises data storage coupled to store and provide data; a data shifter coupled to the data storage to at least bit shift the data obtained from the data storage; and a control circuit coupled to the data storage and the data shifter for controlling a transfer of the data from the data storage and the data shifter. The control circuit comprises a state machine for controlling operation of the data storage and the data shifter; and the state machine is programmable responsive to code executable by a processor coupled to an auxiliary processing unit to adapt to the auxiliary processing unit.

Abstract: A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: An impedance matching circuit has a number of buffers each having a variable impedance circuit. A variable impedance sense control block has an impedance code as an output. A sequencing circuit couples the impedance code of the variable impedance sense control block to the variable impedance circuit of each of the buffers.

Abstract: Disclosed is an oscillator circuit, comprising a crystal oscillator, an amplifier having an input and an output coupled across the crystal oscillator, a comparator having a reference input and an input coupled to the crystal oscillator and a pole network coupled between the comparator and the amplifier.

Abstract: A method and apparatus for adjusting PLL and/or DLL timing offsets have been disclosed.

Abstract: A voltage-controlled oscillator operates at high frequency without high gain by dividing the frequency range into a plurality of subranges, which preferably are substantially equal in size. Within any subrange, the full extent of variation in the control signal changes the frequency only by the extent of the subrange. The gain is thus substantially equal to the gain one would expect for the full frequency range, divided by the number of subranges. The subrange may be selected manually, or by an initial calibration process. In one embodiment, the oscillator includes a voltage-to-current converter and a current-controlled oscillator, with a current mirror arrangement. In that embodiment, selection of the subrange may be controlled by turning on the correct number of current legs.

Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

Abstract: An improved interface circuit is provided herein for translating a relatively high input voltage into a relatively low output voltage using only low voltage transistors and a single, low voltage power supply. According to one embodiment, the interface circuit includes a power supply, a pair of input transistors with source terminals coupled together for receiving a relatively low voltage from the power supply, and a current sense amplifier with a pair of input terminals, each coupled to a drain terminal of a different one of the pair of input transistors for receiving a pair of differential currents and for generating a pair of differential voltages therefrom.

Abstract: A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 5, a barrier gate circuit 2 and a holding circuit (MMP1, MMP2). The level converter circuit converts a signal level of a circuit operating in a VDD1 system to a signal level of a VDD2 system. The barrier gate circuit is responsive to a standby signal (STBY) to fix input signals (AB, AAB) of the level converter circuit 5 at a LOW level. The holding circuit holds an output of the level converter circuit 5 at a constant voltage when the input signals (AB, AAB) are at the LOW level (FIG. 1).

Abstract: A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.

Abstract: Circuits for implementing logic replication in self-timed integrated circuits are provided. An exemplary circuit includes first and second copies of a replicated circuit, an input circuit, an output circuit, and a pipelined routing path. The first and second copies each have a self-timed input and a self-timed output. The input circuit provides a self-timed input signal alternately to the self-timed inputs of the first and second copies. The output circuit receives the self-timed output from the first copy and the self-timed output from the second copy, and outputs a selected one of the self-timed outputs based on a value of a self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit. The number of pipeline stages in the pipelined routing path can be different from, e.g., less than, the number of stages in both the first and second copies.

Abstract: Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.

Abstract: High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.

Abstract: System and method for providing live insertion. According to an embodiment, the present invention provides an integrated circuit. The integrated circuit includes a first port configured to be electrically coupled to a pad. The first port includes a first connection, a second connection, and a third connection. The integrated circuit also includes a first resistor having a first terminal and a second terminal. Additionally, the integrated circuit includes a second resistor having a third terminal and a forth terminal. The integrated circuit additionally includes a voltage source configured to provided a first voltage. The integrated circuit further includes a first PMOS transistor having a first gate terminal, a first drain terminal and a first source terminal. In addition, the integrated circuit includes a second PMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal.

Abstract: Circuit for selectively using static or dynamic select signals inside an integrated circuit, including a first transistor connecting a static select signal to a dynamic route select output line when a dynamic select CRAM signal is at a first logical level, and a second transistor connecting a dynamic select signal to the dynamic route select output line when the dynamic select CRAM signal is at a second logical level. The circuit further comprises a dynamic select CRAM register that contains a logical value to indicate whether the dynamic select signal bypasses the static select signal. The dynamic select CRAM register is connected to the second transistor gate, and to an inverter whose output is connected to the first transistor gate.

Abstract: An input and/or output pad is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad comprises a pad cell comprising a pad block connected to an input buffer and/or an output buffer and arranged to be connected to one of the core input and/or output pins. The pad also comprises a pad logic module comprising a first and/or a second boundary scan cell, connected to the pad block through the input buffer and/or output buffer and arranged to feed input signals to and/or deliver output signals from the pad block, and control means connected to the first and/or second boundary scan cell(s) and adapted to receive control signals for controlling access to the first and/or second boundary scan cell(s) and feeding the first boundary scan cell with the input signals and/or outputting the output signals delivered by the first boundary scan cell.

Abstract: I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

Abstract: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bi-directional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.