Abstract: In one embodiment, a digital signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic units (ALUs) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.

Abstract: Quotient digit selection logic using a three-bit carry propagate adder is presented. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact. The enhanced quotient digit selection logic chooses a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a four bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fourth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit.

Abstract: A leading-zero anticipator having an independent sign bit determination module is disclosed. An apparatus for anticipating leading zeros for an adder within a floating-point processor includes a leading-zero anticipator and a sign determination module. The leading-zero anticipator generates a leading zeros string and a leading ones string by examining carry propagates, generates, and kills of two adjacent bits of two input operands of the adder. The leading zeros string is intended for a positive sum, and the leading ones string is intended for a negative sum. Independent of the leading-zero anticipator, the sign determination module determines a sign of the output of the adder in concurrence with the operations within the leading-zero anticipator.

Abstract: A Finite Impulse Response filter (FIR) reduces the effect of baseline wandering of the input signal on convergence. The FIR includes an adder, a DC-Insensitive error calculator, a DC-Insensitive coefficient calculator, and a multiplier. The adder adds a first tap signal to a second tap signal to produce a FIR output signal. The DC-Insensitive error calculator calculates from the FIR output signal an error value that converges to zero while the FIR output signal is subject to baseline wandering. The DC-Insensitive error calculator represents the error value via an error signal. The DC-Insensitive coefficient calculator calculates a coefficient value based upon the error signal and an input signal. The DC-Insensitive coefficient calculator forces the coefficient value to converge to a steady state value while the input signal is subject to baseline wandering. The coefficient value is represented by a coefficient signal.

Abstract: An apparatus and method are provided for synthesizing a variable frequency sinusoidal waveform. The apparatus and method exploit octant symmetry properties of sine and cosine waveforms, when taken together. The digital frequency synthesis apparatus includes a phase signal and a phase-to-amplitude converter. The phase signal indicates a desired phase angle of the sinusoidal waveform. The phase-to-amplitude converter is coupled to the phase signal. The phase-to-amplitude converter provides a desired amplitude sample corresponding to the desired phase angle, where the desired amplitude sample is derived from amplitude samples corresponding to an octant of the sinusoidal waveform. The phase-to-amplitude converter includes a Haar Transform-based coarse octant amplitude sample generator that computes Haar coefficients corresponding to the phase signal and transforms the Haar coefficients into the desired amplitude sample.

Abstract: Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies fout without requiring a corresponding increase in the rate fclk at which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency fclk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step &phgr;s.

Abstract: A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.

Abstract: A four-input to two-output adder is disclosed. The four-input/two-output adder includes a sum-lookahead full adder and a modified full adder. The sum-lookahead full adder includes an XOR3 block and an AXOR block for receiving a first input, a second input, a third input, and an input from a forward adjacent adder to generate a first sum signal and a sum-lookahead carry signal, respectively. The modified full adder includes an XOR2 block and a MUX2 block for receiving the first sum signal from the sum-lookahead-full adder, a fourth input, and a sum-lookahead carry signal from a backward adjacent adder to generate a second sum signal and a carry signal, respectively.

Abstract: A polynomial expansion of the z-transform characterization of an n'th order differentiator component's output is utilized to implement a differentiator having reduced gates. The differentiator component comprises at least one adder and a plurality of latches, both having inputs and outputs. The connection of the inputs and outputs is dependent on a polynomial expansion of the z-transform characterization of the differentiator components output. A method of reducing gates in an Nth order differentiator component includes characterizing the differentiator component's output by a z-transform. A polynomial expansion of the z-transform characterization is used to implement a differentiator. A differentiator that is implemented based on a polynomial expansion utilizes fewer gates to achieve the same mathematical function.

Abstract: The invention provides a method and system for computing transcendental functions quickly: (1) the multiply ALU is enhanced to add a term to the product, (2) rounding operations for intermediate multiplies are skipped, and (3) the Taylor series is separated into two partial series which are performed in parallel. Transcendental functions with ten terms (e.g., SIN or COS), are thus performed in about ten clock times.

Abstract: A method and apparatus for calculating a quotient from a dividend and a divisor, wherein the divisor can be represented as (2N+2M) where N is greater than M, and wherein the dividend comprises an X-bit binary number divisible by the divisor without a remainder. The values of N and M for the dividend are determined such that the divisor is equal to the value (2N+2M). The M-th through the (N−1)-th bits of the dividend are selected as lower order bits of the quotient. The (N−1)-th and the (2N−M−1)-th bits of the dividend are examined. If the (N−1)-th bit of the dividend is “1” and if the (2N−M−1)-th bit of the dividend is “0”, then one is subtracted from a value represented by the (2N−M)-th through the (X−1)-th bits of the dividend to obtain a result as higher order bits of the quotient. Otherwise, the (2N−M)-th through the (X−1)-th bits of the dividend are selected as higher order bits of the quotient.

Abstract: On the basis of a high degree of theory, prime numbers are derived through effective processing and steps so as to achieve a remarkable reduction in the processing time taken for the derivation. With respect to an arbitrary prime number rank entered, (1) numerical values are added in sequence to a prime number of the anterior rank to calculate prime number candidates of the next rank; (2) the thus calculated prime number candidate is divided by known prime numbers to verify whether it is a prime number or not; and (3) processing for reducing the verification time is iterated when the thus calculated prime number candidate is larger than a certain value, to thereby derive prime numbers until the entered rank is reached.

Abstract: A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.

Abstract: In order to provide an approximate solution having high accuracy to a given partial differential equation made up of one of a Poisson equation, diffusion equation or other partial differential equation similar in form to a Poisson or diffusion equation, the given equation being applied on a plurality of grid points dispersed at irregular intervals, a program is generated in which not only the dependent variable of the original equation is used, but in addition first order derivatives thereof also are input independently as additional dependent variables, the program thereby serving to execute and solve discretized equations using discretized expressions made up of high accuracy second and third order derivative terms of a dependent variable of the given partial differential equation.

Abstract: A floating-point multiply accumulate method acquiring a final mantissa result comprises comparing exponents of (A*B) and C. Transferring part of the C mantissa to a CHI register. Shifting any part of the C mantissa which overlaps the range of the (A*B) mantissa to align the bits of the (A*B) and C mantissas. Adding the shifted part of the C mantissa to the (A*B) mantissa. Shifting least significant bits corresponding to a number of bits transferred to the CHI register out of the Temp. Result. Mask merging bits of the C mantissa which were transferred to the CHI register with most significant bit positions of the shifted Temp. Result. Rounding this mantissa result to the first precision and acquiring L from an Lbit value of the CHI register or an Lbit value of the Temp. Result based on the bit value of the merge mask corresponding to the Lbit position.

Abstract: In a floating point execution unit capable of executing arithmetic operation at high speed, a canceling prediction circuit (60) inputs directly operands before processing of selectors (2 and 3) and predicts a canceling generated in a subtraction result of the operands executed by a subtraction unit (5). The canceling prediction circuit (60) performs the canceling prediction without waiting the completion of carry adjustment of the operands executed by selecting and then executing the selectors (2 and 3). In addition, the prediction error detection circuit (100). Accordingly, when the subtraction result of the subtraction circuit (5) is output through a selector (12), or before the subtraction result is output, the canceling prediction can be executed. Thereby, the left shifter (8) can execute normalization operation for the subtraction result.

Abstract: A floating-point arithmetic device, including a significand output circuit for calculating a difference between exponents, outputting a first significand with a larger exponent, and shifting the remaining significand by the calculated exponent difference, a first bit inverter, an adder, a leading-zero anticipation circuit for anticipating the consecutiveness of leading zeros from the significands, a leading-zero counter for counting the anticipated number of leading zeros, a left shifter for shifting an output value from the adder, a second bit inverter for taking two's complement of an output value from the left shifter, an incrementer for incrementing an output value from the second bit inverter by one, a compensation shifter for shifting an output value from the incrementer, an exponent subtracter for subtracting the number counted by the leading-zero counter from the larger exponent, and a decrementer for decrementing an output exponent from the exponent subtracter by one.

Abstract: An exponent preprocessing unit preprocesses an n-bit exponent k and exponentiates a base A by the preprocessed exponent k. A bit string storing unit stores a bit string including a sign bit and the exponent k. A reading unit reads a bit pattern composed of the sign bit and a bit sequence made up of a predetermined number of bits. A bit pattern generating unit generates a new bit pattern from the read bit pattern. An operation pattern specifying unit specifies an operation pattern based on the read bit pattern. An operating unit performs an operation according to the specified operation pattern and writes the new bit pattern over the previous bit pattern. The reading unit reads a next bit sequence starting from a different bit in the bit string storing unit. A repeat controlling unit repeats these procedures n+1 times.

Abstract: Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagate signals and carry-skip cells for bypassing certain bit positions with dual-wire differential signal paths to provide high-speed processing of adding operations.

Abstract: The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T0, T1, and T2. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.