Abstract: An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.

Abstract: An encryption/decryption method performs an exponentiation operation on a base number where both the base number and the exponent may be large numbers (i.e., anywhere from 100 to several thousand bits long). The exponent is expressed as a bit string. The bit string is then re-coded utilizing the signed digit algorithm. Predetermined substring patterns are then extracted from the exponent utilizing a string replacement method and compared to a previously constructed look-up table containing exponent values for only a relatively small number of predetermined substrings. The value returned from the look-up table is the base value raised to the power represented by the substring. A pointer for each matching substring in the exponent is stored. The remaining bits in the exponent and intermediate values and are then processed with the base value using a multiply chain algorithm to determine the value of the base raised to the exponent.

Abstract: The inventive mechanism encodes the carry in as well as the operand bits for each place in a binary addition of two streams of bits. The carry ins are encoded as Propagate (Pin), Kill (Kin), and Generate (Gin), with respect to the carry in to a block of bits. Only one of the signals would be high at any time, and the other two would be low. The Pin signal for a bit is true where the bit has a carry in that is the same as the carry in to the block of bits, i.e., the carry in to the block is propagated up to the particular bit. The Kin signal for a bit is true where a carry in to the bit is zero regardless of the carry in to the block, i.e., any carry in to the block is killed before it gets to the bit. The Gin signal for a bit is true where the bit has a carry in of one regardless of carry in to the block, i.e., the carry in to the bit is generated within the block. These signals are used in the calculation of the sum of the operand bits.

Abstract: A fast Hadamard transform device is provided which prevent from increasing of circuit scale and shorten a developing TAT even if the number of bits to be operated. The device includes n of shift register units and n/2 of butterfly computation units. Input data are entered to the shift register units in response to a signal and data stored in the shift register units are supplied as quantized data by providing a signal for each “log2n*(p+log2n)” clocks.

Abstract: A discrete cosine transformation apparatus comprises a transposition section that transposes input picture signal of N×N pixels in every N pixels between the one-dimensional processing and the two-dimensional processing and a transformation section that subjects an output of the transposition section to a discrete cosine transformation.

Abstract: A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a carry-save adder for adding said carry-save partial products and an accumulatd sum to produce a carry and save values; a carry-lookahead adder for adding said carry and save values to produce a product value and a carry-out value; a general purpose adder for adding said carry-out and said product value to produce said final product.

Abstract: A method of performing a FFT of a sequence of N=Bn numbers, where B is a power of 2 and n is a positive integer. A pattern of storage locations for the Bn numbers in M in-place memories is selected recursively, where M is a power of 2 that is less than B, wherein, if n=1, each in-place memory has storage locations for a different B/M of the B numbers, and wherein, if n is greater than 1, the pattern for storing Bn numbers is a concatenation of B patterns for storing Bn−1 numbers, there being B/M successive sets of the patterns for storing Bn−1 numbers in the pattern for storing Bn numbers when n is greater than 1, the patterns, for storing Bn−1 numbers, within each of the B/M successive sets, is mutually identical and is different from the patterns, for storing B numbers, of any other the set. The numbers are stored in the storage locations. An in-place radix-B DFT is performed on each of N/B groups of values stored in the storage locations.

Abstract: A random number generator seeding method and apparatus which includes the provision of an RNG seed register and means for capturing a current count number from one or more fast running counters contained within the apparatus upon the occurrence of an act or acts by an apparatus operator as he performs the normal set-up and initialization function. In the preferred embodiment means are provided for sensing particular acts of the operator, and upon detection of each such “event”, one or more of the counters within the system are read and the count value is appended to previously captured counter values until the desired seed length is obtained. At this time, the RNG is said to be seeded, the initialization phase is completed and the apparatus may be made available to players to commence game play or other use of the apparatus.

Abstract: Apparatus for determining a remainder of a modulo division of a binary number made up of a string of bits, including a first plurality of substantially similar cells coupled in a linear sequence, the first plurality of cells including at least a first cell and a last cell. Each cell of the first plurality includes a second plurality of binary input terminals, the input terminals of the first cell being coupled to receive a pre-determined input, and a second plurality of binary output terminals, each coupled, except for the output terminals of the last cell, to a respective one of the input terminals of a subsequent cell in the sequence. Each cell of the first plurality further includes a control input terminal, coupled to receive one of the bits in the string corresponding to a position of the cell in the sequence. The remainder is generated at the output terminals of the last cell in the sequence.

Abstract: An integrated circuit has a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than five. The two dimensional pyramid filter, in operation, capable of producing, on respective clock cycles, pyramid filtered output signals corresponding to output signals produced by fourteen one-dimensional pyramid filters of order 2N−1, and pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(N−1)−1] using signal sample matrices of order [2(N−1)−1]. The respective output signals in said two-dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.

Abstract: A filter is disclosed for recursive state estimation of a process by matrix factorization. The filter preferably takes the general form of P=XY, where P is a matrix of previous state and/or current observations, Y is a matrix of functions that are used to model the process, and X is a coefficient matrix relating the functions in matrix Y to the previous state and/or current observations of matrix P. Given the previous state and/or current observations, a value for matrix Y can be computed from which a current state estimate can be recovered.

Abstract: A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator and to simplify derivation of resulting discrete samples. In particular, an inverse relationship between weights applied to two samples is recognized and exploited. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight is associated with a second of the samples and a weight which is equivalent to the first weight is associated with the second sample and a weight which is equivalent to the second weight is associated with the first sample. The inverse relationship is exploited by forming two composite weights of the first and second weights and weighting composite sample signals with the composite weights. A first of the composite weights has a value which is one-half of the sum of the values of the first and second weights. A second of the composite weights has a value which is one-half of the difference of the values of the first and second weights.

Abstract: The invention relates generally to radix-r FFTs (Fast Fourier Transforms), and more particularly to a method and an apparatus for assigning data samples to memory when computing a radix-r FFT. In one embodiment, the apparatus comprises a plurality of memory banks for storing the data samples, a memory bank counter indicating the memory banks, a data sample counter for counting an increment of the data samples, a region difference counter for counting a region difference change of a butterfly stage, a computer program having the current values of the data sample counter and the region difference counter as input values for determining whether the fractional part of the current data sample value divided by the current region difference value equals zero, and a multiplexer for multiplexing the current data sample to an assigned memory bank if the fractional part is not equal zero.

Abstract: A method of factoring numbers in a non-binary computation scheme and more particularly, a method of factoring numbers utilizing a digital multistate phase change material. The method includes providing energy in an amount characteristic of the number to be factored to a phase change material programmed according to a potential factor of the number. The programming strategy provides for the setting of the phase change material once for each time a multiple of a potential factor is present in the number to be factored. By counting the number of multiples and assessing the state of the phase change material upon execution of the method, a determination of whether a potential factor is indeed a factor may be made. A given volume of phase change material may be reprogrammed for different factors or separate volumes of phase change material may be employed for different factors.

Abstract: A system and method for accelerating least-mean-square algorithm-based coefficient adaptation which executes in one machine clock cycle one tap of the least-mean-square algorithm including data fetch, coefficient fetch, coefficient adaptation, convolution, and write-back of a new coefficient vector. A data memory stores an input signal. A coefficient memory stores a coefficient vector. A multiplication and accumulation unit reads the input signal from the data memory and the coefficient vector from the coefficient memory to perform convolution.

Abstract: A method for producing a plurality of successive output data values defining an output curve that approximates an input curve defined by a plurality of input sample values, the output data values having a higher sampling frequency than the input sample values, the method comprising the steps of: pre-emphasizing the plurality of input sample values; defining successive and overlapping intervals including at least three of the pre-emphasized input sample values; interpolating a plurality of the output data values in an interpolation interval by calculating a moving average of a linear interpolation curve based on the at least three pre-emphasized input sample values, each of the output data values being influenced by the at least three pre-emphasized input sample values; and, emphasizing differently the influence of the at least three pre-emphasized input sample values for determining different ones of the output data values in the interpolation interval, whereby the pre-emphasizing step brings the output curve

Abstract: A method and system is disclosed for design and implementation of fixed-point filters from floating-point filters. A design sequence for designing a fixed-point filter for a system is selected. A low-order floating-point filter and a first set of parameters associated with the low-order floating-point filter components are then selected. One or more parameters of the first set of parameters is then iteratively modified to obtain a set of modified parameters, until a plurality of performance characteristics calculated using the first set of parameters meets a performance objective for the fixed-point filter for the system.

Abstract: The present invention relates to an apparatus for determining the sum of first and second optical binary words. The apparatus uses a first optical logic gate and a second optical logic gate to generate respective first and second combination words which represent a logical combination of the binary words applied to the respective logic gates. The first and second combination words are then offset by one bit slot with respect to each other by an offsetting device to generate first and second offset combination words. These offset combination words are repeatedly fed back to the first and second logic gates. The binary sum of the original two words is given by the first combination word when each bit slot of the second combination words has the same logical state.

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.