Abstract: A frequency interleaving circuit frequency-interleaves main signals generated according to sound data by parameters set according to frequencies of transmission channels. A sub-signal generating circuit generates sub-signals for transmission control including pilot signals. Mapping circuits modulate the sub-signals by using pseudo-random sequences generated based on initial values of random codes set according to frequencies of transmission channels. The frequency-interleaved main signals and the sub-signals modulated by the mapping circuits are OFDM-modulated. Then, they are converted to the frequencies of the transmission channels. An increase of a dynamic range of transmission signals can be suppressed by controlling the initial values of random codes set.

Abstract: A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.

Abstract: A filter arrangement with a linear phase characteristic having first filter cascade coupled to second filter. The first filter is an analog or digital filter designed so that its amplitude characteristic meets a predefined amplitude specification. The second filter is implemented as the anti-causal version of a fictive digital all-pass filter that is designed so that its phase characteristic, up to a linear function of frequency, equals the phase characteristic of the first filter.

Abstract: A method and apparatus for initial acquisition using an adaptive threshold includes performing a sort operation of a plurality of full-length correlator outputs and updating the adaptive threshold. Partial-length correlator outputs are generated and compared with an adaptive threshold. If a partial-length correlator output for a particular PN sequence timing is greater than or equal to the adaptive threshold, a full-length correlator output for that PN sequence timing is generated. A sort operation of a plurality of full-length correlator outputs is performed, and sort results are used to update the adaptive threshold. If a partial-length correlator output for a particular PN sequence timing is less than the adaptive threshold, a full-length correlator output for that PN sequence timing is not generated.

Abstract: A direct sequence spread spectrum system consisting of modulator and demodulator wherein the spreading sequence with zero correlation zone properties, and the despreading consists of multiplying the received signal with the same spreading sequence, followed by a low pass filter, decoder and deinterleaver. The bit rate of the spreading sequence for each user is normally much higher than the input encoded data bit rate, and therefore it spreads the system spectrum.

Abstract: A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (FLO) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).

Abstract: The invention concerns generally the technology of reducing frequency offset in a radio receiver. Especially the invention concerns receivers where a channel estimator is used for correcting the base band signal. The objects of the invention are achieved by monitoring the phase of the channel estimation output and generating a complex phasor on the basis of successive phase values. The received baseband signal is then multiplied by the generated complex phasor for compensating the frequency offset. The frequency compensation can be made before or after said channel estimation thus producing a feedback compensation or feed forward compensation. The feedback compensation can be implemented by compensating the baseband signal either prior to the despreading or after the despreading.

Abstract: A reduced rank adaptive digital filtering method is described for a received signal consisting of a sequence of N×1 received vectors. Each received vector is formed from a group of N successive samples. D+1 basis vectors are generated where D is less than N and the dimension of a desired reduced rank subspace. Each successive basis vector is generated by multiplying an immediate preceding basis vector by the covariance matrix for the sequence of received sample vectors and the first basis vector is formed from a given or estimated steering vector. D filter coefficients are generated from correlations between pairs of basis vectors. The adaptive digital filter of the present invention achieves near optimal rank performance with substantially fewer training symbols than heretofore possible.

Abstract: A CDMA baseband receiver includes a first correlating unit, a long code phase candidate outputting section and a long code determining section. The first correlating unit calculates first correlation values from a spread modulation signal and a short code which is common to base stations. The long code phase candidate outputting section outputs selected long code phase candidates corresponding to ones selected from the first correlation values, based on the spread modulation signal, and determined long codes. The selected long code phase candidates are other than long code phase candidates for known ones of the base stations. The long code determining section generates the determined long codes for unknown ones of the base stations from the spread modulation signal, the short code, and long codes generated based on the selected long code phase candidates. Each long code is peculiar to one base station.

Abstract: A method for channel equalization of received data includes steps of: receiving the received data in a received data packet; calculating filter setting coefficients for an input filter and calculating equalizer setting coefficients for an equalizer; setting the input filter using the filter setting coefficients and setting the equalizer using the equalizer setting coefficients; equalizing the received data using the input filter and using the equalizer; determining channel parameters for the transmission channel from the received data Xk; storing the channel parameters in a data field; and performing the step of calculating the filter setting coefficients for the input filter and calculating the equalizer setting coefficients for the equalizer by performing a GIVENS rotation of the data field.

Abstract: A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

Abstract: A packet signal, formed according to an orthogonal frequency division multiplexing (OFDM) format, received by a receiver is decoded in a decoder device of the receiver. The packet signal includes a data code and a control code having a formula for decoding the data code. The control code is first decoded and analyzed to obtain the decoding formula contained therein. The data code is decoded during a period in which the control code is being analyzed, based on plural decoding formulae one of which coincides with the decoding formula contained in the control code. Data signals decoded based on the respective decoding formulae are sent to an output selector together with the decoding formula obtained from the control code. The output selector selects a data signal which is decoded based on a decoding formula that coincides with the decoding formula obtained from the control code.

Abstract: A receiver detects a highly precise approximate value of the power of a reception signal with a high speed. A first comparator outputs a larger of a component I and component Q of a reception signal as a first output value and a smaller as a second output value. A 3-bit shift register multiplies the first output value by ?, a subtractor subtracts the by-?-multiplied value from the first output value, and a 1-bit shift register multiplies the second output value by ½. A 2-bit shift register multiplies the by-½-multiplied value by ¼, a first adder adds the first output value and the by-¼-multiplied value, and a second adder adds an output value from the subtractor and an output value from the 1-bit shift register. A second comparator outputs the value of a larger result of the two additions as an approximate power of the reception signal.

Abstract: In a clock-pulse supply unit, a first receiver unit is used to tap a central system clock pulse from the back panel. A time delay occurs in the first receiver unit. In order to compensate this time delay, a second receiver unit is used which is identical in construction to the first receiver unit and has the same time delay as the first receiver unit. A redundant clock pulse is supplied to the second receiver unit and thereby undergoes the same time delay as the central system clock pulse in the first receiver unit. The central system clock pulse and the redundant clock pulse can then be accurately compared with one another in a phase detector. The redundant clock pulse is then synchronized to the central clock pulse. The switchover from a slave clock pulse to the redundant clock pulse is effected only when synchronization is completed.

Abstract: A system for automatic gain control prevents input overload by precisely controlling the input level of a received, digitally modulated signal without using a variable gain amplifier. A limiting amplifier in conjunction with a logarithmic detector splits an input signal path in two, providing separate phase and amplitude information for downstream digital signal processing, where the separate phase and amplitude information is processed without variable gain artifacts. The separated phase information may further be divided into I and Q signals.

Abstract: A rain attenuation compensation method that includes estimating a signal-to-noise (S/N) ratio from PSK-modulated receiving signal at a receiving end; predicting a signal-to-noise (S/N) ratio of the next time point on the basis of the signal-to-noise (S/N) ratio values of the past and present time points; and determining which of transmission methods is adequate to the predicted signal-to-noise (S/N) ratio of the next time point. If the switching of the transmission method is determined, a control signal for inquiring the change of the transmission method is transmitted to a transmitting and a receiving end. Data is then transmitted by the switched transmission method.

Abstract: Methods of recovering information encoded in a spread spectrum signal transmitted according to a spreading sequence in a communications medium are provided in which a spread spectrum signal is received from the communications medium and correlated with a spreading sequence to produce a plurality of time-offset correlations. Some of these time-offset correlations may be designed to cancel out known interfering signals. A subset of the plurality of time-offsets may then be selected, and corresponding traffic correlations may then be combined using a weighted combination to estimate information encoded in the transmitted spread spectrum signal. Receivers for implementing these methods are also provided.

Abstract: A radio receiver architecture is disclosed which has first and second front end circuits optimized for reception in two frequency bands. Each front end circuit includes a mixer for downconverting received signals to a respective intermediate frequency. Signals from the two front end circuits are passed to a single analog-to-digital converter. The sampling rate of the analog-to-digital converter and the intermediate frequencies are chosen such that the received signals appear at the same point in different teeth of the alias response of the analog-to-digital converter.

Abstract: Spread spectrum packet-switching radio devices (22) are operated in two or more ad-hoc networks or pico-networks (19, 20, 21) that share frequency-hopping channel and time slots that may collide. The frequency hopping sequences (54) of two or more masters (25) are exchanged using identity codes, permitting the devices to anticipate collision time slots (52). Priorities are assigned to the simultaneously operating piconets (19, 20, 21) during collision slots (52), e.g., as a function of their message queue size or latency, or other factors. Lower priority devices may abstain from transmitting during predicted collision slots (52), and/or a higher priority device may employ enhanced transmission resources during those slots, such as higher error correction levels, or various combinations of abstinence and error correction may be applied. Collisions are avoided or the higher priority piconet (19, 20, 21) is made likely to prevail in a collision.

Abstract: A system and method for inverting automatic frequency control applied to a reference signal used to process an input signal is disclosed. When receiving an input communication signal, a receiver controls the frequency of the reference signal to compensate for frequency differences between a transmitter and a local oscillator in the receiver. The frequency control applied to the reference signal causes frequency variations in a resultant signal processed signal when the input signal is processed using the reference signal. The frequency of a second reference signal is controlled such that further processing of the resultant processed signal removes effects of the frequency control applied to the reference signal. The processing which applies frequency control to the reference signal is performed in real time while the inversion process is performed in a separate processing section.