Abstract: What is described here is an array for the transmission of electrical energy or signals, respectively, between a base station and several external units adapted to be coupled, without contact, to various positions on said base station. The invention is characterised by the provisions that the primary side circuitry of a power supply with potential isolation is provided on each connecting position of the central unit, and that each of said external units includes the corresponding circuitry of the secondary side, with the power transmission being realised via an inductive coupler element that replaces the transformer that is usually used in such a power supply, and that the feedback signals are transmitted by means of a further non-contacting coupler element from said external units back to said base unit.

Abstract: An apparatus, system, and corresponding method for acquiring a spread spectrum signal, where the acquiring includes matching the phase of a replica of a code component to the phase of the received code component and also determining the carrier frequency including any Doppler or other shifting, the apparatus including: a multi-section matched filter for providing successive section outputs each including elements corresponding to a different replica code phase; and a compensated acquisition module, responsive to each section output of each of the sections, for providing a sequence of frequency indicators, each corresponding to a different frequency offset, with each section output having elements each of which corresponds to a particular value of replica code phase, wherein each frequency indicator is based on a combining, phase element-wise, of the section outputs using compensating factors that depend on the corresponding frequency offset.

Abstract: Signal component converging section 105 delays received signal components spread on a time axis to combine signal components based on an output of propagation path estimating section 104, maximum value detecting section 106 detects a sample timing of a signal component with the maximum power among signal components combined in signal component converging section 105, and tap coefficient estimating section 107 estimates a tap coefficient that minimizes a mean square of a difference between a replica signal and a received signal while assigning a tap coefficient of a fixed value (for example, 1) to a sampling timing providing the maximum power, and outputs the estimated tap coefficient to FFF in plural array combining section 102 and a replica generating section in Viterbi equalizer 108.

Abstract: A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.

Abstract: A parallel distributed sample acquisition system is disclosed. It is capable of carrying out parallel distributed sample acquisition employing M-ary signaling for fast synchronization of a diffusion band signal and a signal acquisition method using the same. The system includes a transmitter for taking at least one or more first state samples at the same time from a first main sequence for data spreading and spreading the first state sample to an M-ary symbol state signal, thereby transmitting the state signal, and a receiver for detecting the first state sample from the transmitted state signal, comparing the first state sample detected with a second state sample taken from a second main sequence for data despreading, and correcting the state of the second main sequence in accordance with the compared result, thereby enabling the synchronizing to the first main sequence.

Abstract: The specification discloses a cancellation circuit that suppresses electromagnetic interference in a high speed circuit using a function generator so as to utilize differential signals to cancel the magnetic field and to couple with the electric field without affecting the quality of signals. The differential signals are generated from a clock pin of the function generator, which is phase shifted by a phase shifter and passes through a microstrip antenna or a stripline antenna so as to emit electromagnetic waves with inversed phases, canceling the originally existent electromagnetic waves.

Abstract: The invention relates to a frequency hopping method and a base station including, at the receiver end, a number of baseband processing units and broadband receiver units, which form RF sub-bands and receive frequency hopping signals according to a frequency hopping sequence from the RF sub-bands they have formed. The base station includes, at the receiver end, a switching device and channelling unit, which receive baseband signals from an intermediate band and each of which is connected to a receiver unit forming a particular RF sub-band. The switching device selects, according to the frequency hopping sequence, the channelling unit whose baseband output provides the baseband signal which is connected to the baseband processing unit. The channelling unit places the baseband signals to its baseband output according to the frequency hopping sequence.

Abstract: A transmitter circuit for transmitting a sine wave modulated with digital data, where the sine wave includes a clock signal, and a receiver circuit for demodulating the transmitted sine wave, where the receiver circuit extracts the clock signal and the digital data from the sine wave. The transmitter circuit includes digital logic components that allow the transmitted sine wave to include at least one bit per cycle of the sine wave, and the receive circuit includes digital logic components that allow the clock signal and the digital data to be extracted from the sine wave. In various embodiments, the transmitted sine wave includes one bit per cycle, one bit per half cycle, multiple bits per cycle and multiple bits per half cycle.

Abstract: A system and method of timing estimation for use in a digital receiver within a communication system. An algorithm calculates the timing offset by evaluating the spectral component at the symbol clock frequency. The spectral component is generated using a nonlinearity operation. However, the maximum likelihood non-data-aided timing estimation equation reveals an alternative approximation for the logarithm of the hyperbolic cosine function present in the maximum likelihood equation, which offers a compromise between implementation complexity and variance performance. The estimated timing offset is then fed to a timing correction unit, which calculates the data samples corresponding to the sampling clock phase and removes the redundant samples. The ideal sampled signal is then forwarded to additional synchronization and functional units for further processing.

Abstract: A transceiver has bidirectional internal interface lines which can be connected to a baseband circuit. The transceiver is switchable by the baseband circuit between a transmission mode and a reception mode. The internal interface lines are connected to at least one quadrature modulator which in the transmission mode is connected to the interface lines, and to a quadrature demodulator which in the reception mode is connected to the interface lines. In the alternative, the demodulator is set to high impedance in the transmission mode and the modulator is set to high impedance in the reception mode.

Abstract: A method and apparatus for receiving data over a dispersive media is disclosed. The received signal is composed of an unknown data segment preceded and followed by known data segments. A replica of each known data segment is generated by the communication apparatus. Channel characteristics existing at the time of transmission of the known data segments are estimated by comparing the known data segments with the replica. Using estimations of the channel characteristics, symbols of the unknown data segment can be determined. Decisions can be made on the various unknown symbols as they are analyzed. Channel characteristics can be re-estimated after determining each symbol, each pair of symbols or each group of symbols. Two solutions of the unknown symbols can be combined in various ways to arrive at a final determination of the unknown transmitted symbols.

Abstract: A peak magnitude of a signal is estimated from a set of signal samples. From the set of signal samples, a largest signal sample and an adjacent next largest signal sample are selected that occurs, respectively, at a time, s1 and at a time, s2. A first ratio of a first derived signal sample and a second derived signal sample is generated, the first derived signal sample being derived from the largest signal sample, and the second derived signal sample being derived from the next largest signal sample. A second ratio is determined from the first ratio, the second ratio representing a peak magnitude of a communication system response divided by a second magnitude of the communication system response, wherein the second magnitude is the communication system response at the time s1. The peak magnitude of the signal is generated from the second ratio and the first derived signal sample.

Abstract: The present invention provides an apparatus and method for universal decoding of both feedforward codes and feedback codes, such as decoding of a 512-state feedforward code, a 32-state feedback code and 8-state feedback code. Utilizing parallel processing, the present invention determines, for each current state of a feedforward or a feedback code, its most likely previous states, resulting in a determination of a terminating state and a penultimate terminating state. From the penultimate terminating state and terminating state, associated subset bits are determined. In the preferred embodiment, the subset bits are determined by re-encoding the most significant bit of the penultimate terminating state in an encoder having a current state equal to the terminating state. Utilizing an equalized, received signal, a closest signaling point, with an associated index, is selected from a subset of a signaling constellation corresponding to the associated subset bits.

Abstract: A memory for data accumulation includes an input on which such data are entered as a stream of input data under the control of an input timing signal and an output starting from which the data entered in memory are read as a stream of output data under the control of a reconstructed timing signal. A phase-locked loop uses this input timing signal as an input signal to generate a corresponding phase-locked output signal. Of such phase-locked loop output. A device is provided to measure residual phase wander and act on the transfer function band of the phase of phase-locked loop output which is preferably without ring filters.

Abstract: The invention relates, in the field of subband decomposition, to the design of filter banks adapted to the input signal statistics. In most cases, two channel filter banks are iteratively applied over several levels of decomposition, the signals in the resulting subbands representing decimated and filtered versions of the input signal. According to the invention, it is proposed a perfect reconstruction critically decimated polyphase filter bank with a ladder structure, which adapts to the nonstationarities in the input signal.

Abstract: A clock recovery circuit provides a reference clock signal and a plurality of clock pulses with phases different from the reference clock signal, and has an edge detecting circuit for detecting positions of edges of inputted serial random data. A detected edge selecting circuit selects whether the edges of the inputted serial random data are rising edges or falling edges of the reference clock signal. An edge position correcting circuit assures that the number of the selected edges is equal to the number of the edges of the inputted serial random data. Phase frequency detectors output pulses of a pulse width in proportion to the phase difference between the inputted serial random data and the reference clock signal.

Abstract: A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.