Abstract: A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to the interrupt is set to an execution-waiting state. An ICB having a highest priority from among the ICBs that are set to the execution-waiting state is selected. A processor context saved in a context saving area of the selected ICB is stored in the stack area. An ISR corresponding to an ICB selected by an interrupt return command is executed.

Abstract: A bus interface permits an upstream bandwidth and a downstream bandwidth to be separately selected. In one implementation a link control module forms a bidirectional link with another bus interface by separately configuring link widths of an upstream unidirectional sub-link and a downstream unidirectional sub-link.

Abstract: A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus; and an internal register in which is set interface information for specifying signal types of the interface signals output from the interface circuit. The interface circuit includes first to Nth interface circuits (N is an integer greater than one), and each of the first to Nth interface circuits generates an interface signal of a signal type according to the interface information set in the internal register.

Abstract: A computer-implemented method of generating timeout errors based on shared register access by two processors is described. A processor access timer is started responsive to generation of an access request by a first processor. The generated first processor access request is transmitted to a shared storage component including a shared register and able to communicate with both the first and second processors. A timeout error is generated responsive to the processor access timer exceeding a processor predetermined timeout threshold value.

Abstract: A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.

Abstract: A data transferring system based on the PCI Express standard in which power saving is realized is disclosed. In the data transferring system, a data transferring device transfers image data based on the PCI Express standard by synchronizing with a line synchronizing signal LSYNC. At this time, the data transferring device causes a period between packets (image data) to be transferred in one line cycle of the line synchronizing signal LSYNC to be shorter than a transition period “t1” which is required to transit from a link state L0 to a link state L0s and from the link state L0s to the link state L0. With this, the number of the transition periods “t1” is reduced and the period of the link state L0s is made long.

Abstract: An architecture for a Block RAM (BRAM) based arbiter is provided to enable a programmable logic device (PLD) to efficiently form a memory controller, or other device requiring arbitration. The PLD arbiter provides low latency with a high clock frequency, even when implementing complex arbitration, by using BRAM to minimize PLD resources required. The architecture allows multiple complex arbitration algorithms to be used by allowing the multiple algorithms to be stored in BRAM. With multiple algorithms, dynamic configurability of the arbitration can be provided without halting the arbiter by simply changing an algorithm stored in BRAM. Additionally, algorithms can by dynamically modified by writing to the BRAM. With BRAM memory used for arbitration, PLD resources that would otherwise be wasted are frees up to be used by other components of the system.

Abstract: Computing systems with conventional CPUs coupled to co-processors or accelerators implemented in FPGAs (Field Programmable Gate Arrays). One embodiment of the systems and methods according to the invention includes a FPGA accelerator implemented in a computer system by providing an adapter board configured to be used in a standard CPU socket.

Abstract: A PCI-E automatic allocation system which essentially consists of a detection module and a switch module, wherein the detection module detects the states of the logic signals on the ground pins of a first PCI-E slot with large lane width and a second PCI-E slot with small lane width in a computer system, to determine whether the first and second PCI-E slots hold any inserted expansion card; if the detection module detects an inserted expansion card in the first PCI-E slot rather than the second PCI-E slot, a switch control signal output is generated, to control the switch operation performed by the switch module, that is, transferring lane availability from the second PCI-E slot to the first PCI-E slot, with a view to enhancing the use of PCI-E lanes, speeding up data transmission, and overcoming a known drawback of PCI-E buses, that is, inflexible design.

Abstract: A method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The method includes detecting an incoming address on the I2C bus, translating the incoming address to an outgoing address, and communicating data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

Abstract: A method for bi-directional transmission of data between a source and a sink over a two-wire interface includes re-mapping a data signal and a clock signal from a first local bus on the source into a different protocol signal. Transmitting the different protocol signal from the source to the sink over the two-wire interface. Re-mapping the different protocol signal back into the data signal and the clock signal for use on a second local bus on the sink. Re-mapping the data signal and the clock signal from the second local bus into the different protocol signal; and transmitting the different protocol signal from the sink to the source over the two-wire interface.

Abstract: The capability to handle the 100 ?s RPR interrupt and similar interrupts is provided by servicing selected interrupts outside of the operating system. This drastically reduces the latency and overhead associated with servicing the interrupt. A method of handling an interrupt in a computer system comprises receiving the interrupt at the computer system, determining whether the interrupt is a selected interrupt, and performing interrupt processing not involving an operating system of the computer system, if the interrupt is a selected interrupt.

Abstract: In various embodiments, a system may include a processor, a host controller coupled to the processor, a Universal Serial Bus (USB) device coupled to the host controller and a non-USB device coupled to the USB device. In some embodiments, the host controller may be configured to communicate with the non-USB device through a small computer system interface (SCSI) pass-through command. In some embodiments, a method may include a host controller sending a SCSI pass-through command to a USB device coupled to a non-USB device, the USB device receiving the SCSI pass-through command, and the USB device interacting with the non-USB device in response to the SCSI pass-through command.

Abstract: A method of notifying clients of a change in a USB including a first client requesting notification of a first change in the USB, detecting the first change in the USB, and notifying the first client requesting notification that the first change in the USB occurred.

Abstract: A method for controlling bi-directional data transfers in an electronic circuit is provided. The method involves when a first of at least two data signals is activated as an originating data signal prior to a second of the at least two data signals: allowing only a device associated with the first of the at least two data signals to be a signal source, and causing a device associated with the second of the at least two data signals to enter a receive state as a signal sink. The method further involves passing at least one bit of data from the signal source to the signal sink.

Abstract: A system and method which efficiently manages the status of resources or services in a document processing system or device and uses a priority-based dynamic allocation process for allocating or releasing selected resources for a user or task. A job resource manager receives resource requests containing a resource name, quantity and order of use. The resource manager then determines if the request meets predetermined parameters, so as to lock the designated resource for use by the job with which the request is associated. The resource is then released for use by the job and remains inaccessible to other jobs until unlocked. The resource is unlocked by the job resource manager upon receipt of notification that the job has been completed.

Abstract: A communication system according to an embodiment of the invention includes: a plurality of communication nodes; and a common bus connected with the plurality of communication nodes, wherein the plurality of communication nodes individually checks a use state of the bus to allow/disallow transmission, and at least one of the plurality of communication nodes includes: a storage circuit storing data representing whether or not a frame follows a first frame sent to the bus; and a control circuit determining, when outputting a second frame after the completion of transmission of the first frame, whether or not to output the second frame to the bus with reference to the data stored in the storage circuit.

Abstract: A multifunctional device extracts identification information items from received device-cloning file data items and determines whether a data restoration process is a backup process or a cloning process based on whether or not a serial number in the identification information items is identical with a serial number in a multifunctional device having received the device-cloning file data items. In the backup process, specific information items and general information items are restored. In the cloning process, only general information items are restored.

Abstract: A bus structure of a mobile communication terminal for reducing digital noise is disclosed. The bus structure comprises a bus switch controller, a first element having a first bus, a second element having a second bus, and a common bus for connecting the first bus and the second bus. A bus switch positioned between the first element and the second element for disconnecting at least one of the first bus and the second bus from the common bus in response to a control signal from the bus switch controller for reducing digital noise of the common bus.

Abstract: Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.