Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2n. In various embodiments, such a transaction identifier combined with a source identifier and a home node identifier may form a globally unique transaction identifier.

Abstract: When four access request origins A, B, C, and D are present, a priority table (No. 1) having a priority order of A, B, C, and D, a priority table (No. 2) having a priority order of B, D, A, and C, a priority table (No. 3) having a priority order of C, A, D, and B, and a priority table (No. 4) having a priority order of D, C, B, and A are prepared. An order of employing these tables is determined in advance in this order. A priority table next in the order to the priority table employed in last arbitration or, when a priority table at the bottom in the order is employed in last arbitration, a priority table at the top in the order is employed. Based on the priority levels defined in the employed priority table, an access request to be accepted is selected.

Abstract: Methods and systems for a low-cost high density compute environment with increased fail-over support through resource sharing and resources chaining. In one embodiment, one of a number of servers qualified to share resources is elected as a resource server. The shared resource can be firmware memory, hard-drive, co-processor, etc. The elected server responds to requests from individual requesters and provides the responses, such as firmware images. In one embodiment, all the blade servers on a rack use an image server for their firmware image so that these blade servers can automatically adopt a common personality across the entire rack. If the elected image server fails, a dynamic process elects an alternate image server. In one embodiment, among a set of qualified servers, only one is actively elected at a given time.

Abstract: Technologies are described herein for governing access to a computing resource. A proxy receives a request to access a computing resource. In response to the request, the proxy determines whether the request can be granted without consulting a governor for the computing resource. If the request cannot be granted without consulting the governor, the proxy transmits the request to a broker. The broker, in turn, transmits the request to a governor for the computing resource. The governor determines whether the requested access to the computing resource should be granted. The governor generates a response to the request and transmits the response to the broker. The broker, in turn, transmits the response to the proxy. The broker may also request notifications from the governor.

Abstract: A method and computer program for implementing a reset both in a master computer and a slave computer which are both connected to a shared data bus. To allow a different reset configuration of both computers even when the slave computer, in particular, has no possibility of an internal slave-reset configuration, the method provides that the slave computer is configured with a slave-reset configuration which is provided to the slave computer by the master computer, reset-configured beforehand, via the data bus.

Abstract: An apparatus, system and method to facilitate I2C communication between a host device and a slave device where the slave device shares a common physical address with another slave device on the I2C bus. The apparatus includes a detection module to detect an incoming address on the I2C bus, a translation module to translate the incoming address to an outgoing address, and a communication module to communicate data between the host device and the slave device where the outgoing address matches the physical address of the slave device. In this manner, the present invention avoids address conflicts between commonly addressed slave devices while reducing costs, components, and complexities traditionally associated with dynamic addressing techniques and other prior art solutions to address conflicts.

Abstract: Various embodiments of the present invention are directed to augmented interrupt controllers (AICs) and to synthetic interrupt sources (SISs) providing richer interrupt information (or “synthetic interrupts” or “SIs”). The AIC and SIS provide efficient means for sending and receiving interrupts, and particularly interrupts sent to and received by virtual machines. Several of these embodiments are specifically directed to an interrupt controller that is extended to accept and deliver additional information associated with an incoming interrupt. For certain such embodiments, a memory-mapped extension to the interrupt controller includes a data structure that is populated with the additional information as part of the interrupt delivery. Although several of the embodiments described herein are disclosed in the context of a virtual machine system, the inventions disclosed herein can also be applied to traditional computer systems (without a virtualization layer) as well.

Abstract: Handling interrupts within an information handling system including entering into an interrupt management mode in response to receiving an interrupt, identifying at least one source of the received interrupt in accordance with an ordered list of a plurality of possible interrupt sources, dispatching an appropriate interrupt handler to resolve the identified at least one source of the received interrupt, noting a frequency of occurrence of each indentified at least one source generating a received interrupt over time, and recording the ordered list of possible interrupt sources in response to the noted frequency, wherein the possible interrupt sources with higher frequencies are placed in the beginning of the ordered list.

Abstract: A method and apparatus for sharing peripheral devices between multiple execution domains of a hardware platform are described. In one embodiment, the method includes the configuration end-point devices, bridges and interconnects of a hardware platform including at least two execution domains. When a configuration requests is issued from an execution domain, the configuration requests may be intercepted. Hence, the received configuration request is not used to configure the peripheral end-points, bridges or interconnects of the hardware platform. Configuration information decoded from intercepted configuration request may be stored as virtual configuration information. In one embodiment, configuration information is read from a target of the configuration request to identify actual configuration information.

Abstract: A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt handler is read from the system memory to begin handling the interrupt signal. A second part of the running task is stored to system memory via direct memory access. The micro interrupt handler is executed and read and the previous running task is read from direct memory access and restored. Long lag times for interrupt processing and inefficiencies in processor queues are avoided.

Abstract: A bus interface and corresponding method is provided for conveying communication signals supporting multiple modes, where at least two of the modes have distinct operational communication signal levels. The bus interface is adapted to convert the communication signals between communication signals having distinct signal levels, and communication signals having compatible signal levels. Where in at least some instances, the conveyed communication signals are converted from communication signals having distinct signal levels to communication signals having compatible signal levels, and then back to communication signals having distinct signal levels, after the communication signals having compatible signal levels are transmitted and received via one or more associated communication paths.

Abstract: A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

Abstract: A method and system for processing received and transmit data by an application specific integrated circuit (ASIC) from a network link. The method for received data includes swapping received data polarity if swap-polarity ability is set and swapping byte lanes for the received data if swap-lane ability is set. The method for transmit data includes swapping byte lanes for transmit data, if swap-byte lane ability is set and swapping data polarity if swap-polarity ability is set. The ASIC includes a network connector that receives and transmits data from the network link.

Abstract: The present invention is directed to an improved memory and I/O bridge that provides an improved interface for communicating data between the data bus of the system processor and the memory controller. The memory and I/O bus bridge according to the present invention provides increased performance in the system. The memory and I/O bridge can include a deep memory access request FIFO to queue up memory access requests when the memory controller is busy. The memory and I/O bridge can include a memory write data buffer for holding and merging memory write operations to the same page of memory. The memory and I/O bridge can include a memory read data buffer for holding and queuing data and instructions read from memory, waiting to be forward to the data bus. The memory data read buffer can operate in one or more software selectable prefetch modes, which can cause one or more pages to be read in response to a single memory read instruction.

Abstract: A method of operating a bus interconnect coupled to bus masters and bus slaves is provided. The method includes receiving a request from a bus master to perform a bus transaction associated with a transaction ID with a bus slave of the plurality of bus slaves, the bus transaction being a first type of bus transaction. The method further includes performing the transaction if a resource allocation parameter allocated to the bus master meets a first threshold. The method further includes if the resource allocation parameter does not meet the first threshold, performing the data transaction only if the transaction meets a condition of a set of at least one condition, wherein a condition of the set of at least one condition includes that the transaction ID of the transaction is not a transaction ID of any outstanding bus transaction of the first type requested by the bus master.

Abstract: Various approaches for tracing events in an electronic system are disclosed. In one approach, a circuit arrangement includes a bus, a random access memory (RAM), a plurality of programmable logic resources, and coupled configuration memory cells. A circuit arrangement is implemented in the programmable logic. The circuit arrangement receives a plurality of event indication signals from an application circuit and writes event data to the RAM in response to a change in the state of any one of the event indication signals. A bus interface circuit is coupled to the bus and to the read port of the RAM. Responsive to a read transaction on the bus for the RAM, the bus interface circuit reads data from the RAM and outputs the data on the bus in a reply bus transaction.

Abstract: An arbiter module receives two or more closely occurring asynchronous requests and provides an output with a low metastability failure probability. The arbiter module includes a request resolving module that receives multiple asynchronous requests for providing a final output. The request resolving module includes one or more arbiter stages cascaded with each other and operatively coupled with logic units.

Abstract: A falling protective device for protecting a hard disk of a falling portable computer against damages includes a falling sensor arranged in the portable computer for generating and sending an interrupt signal to a keyboard controller in response to a detected falling state of the computer. An SMI signal line is extended between and connected to the keyboard controller and a system BIOS of the computer. On receipt of the interrupt signal generated by the falling sensor, the keyboard controller sends an SMI signal via the SMI signal line to the system BIOS, which in turn sends a park control signal to park the hard disk or a power-off control signal to terminate the supply of working power to the hard disk. The system BIOS sends a polling signal via a polling signal line to the keyboard controller, so as to poll about a state signal of a default status bit in a default signal port of the keyboard controller.

Abstract: A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke.