Abstract: A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state.

Abstract: An apparatus and method for reclaiming a portion of random access memory in a personal computer system. The personal computer system comprises a system processor, a memory controller, a random access main memory, a read only memory, and at least one direct access storage device. The read only memory includes operating system microcode. The memory controller regulates communications between main memory and the system processor. In response to signals from the system processor, the memory controller can either execute the microcode out of the read only memory and recover main memory previously used to store the microcode, or disable read only memory, copy the microcode to main memory and execute the microcode out of main memory.

Abstract: A bus access controller. An interface circuit (22) controls the access of a host computer (10) and a microprocessor (23) to one or more UARTs (14, 15). The microprocessor (23), which has no provision for waiting for a data transfer, is required to provide a signal of its intent to perform a data transfer prior to beginning the actual data transfer. The signal is identical to the actual data transfer operation. If the host (10) attempts a data transfer operation while the microprocessor (23) is conducting a data transfer operation, or if the host data transfer cannot be completed prior to the time that the microprocessor data transfer will commence, then the interface circuit (22) signals the host (10) that the data transfer will take additional time by deasserting the I/O READY line (12a). Once the microprocessor data transfer is completed then the I/O READY signal is reasserted and the host data transfer is completed.

Abstract: This invention relates to an arrangement for distributing interrupts within a multiprocessing system and for processing personal computer (PC) interrupts as well as multiprocessor interrupts in that system. New interrupts are diverted from processors that have recently processed an interrupt, thus preventing any one processor from being overloaded with an interrupt processing work load. Some of the processors are equipped to process PC interrupts and multiprocessing system interrupts. In each processor classes of interrupts may be masked out. A distributed arbitrator is used to allocate an interrupt among a plurality of processors available to process the interrupt.