Abstract: A data transfer apparatus comprises a plurality of selectors each having two inputs and an output, and a transfer gate gating the transfer of data, wherein one inputs of the plurality of selectors are connected to respective bits of a data bus in the order that transfer bits are arranged, while the other inputs thereof are connected to the outputs of the other selectors in the order, the transfer gate is connected to the output of the final-stage selector of the plurality of selectors, data of the respective corresponding bits of the data bus is set in the respective plurality of selectors when a transmission enable signal is in a negated state, and when the transmission enable signal is arranged to be in an asserted state, the plurality of selectors and the transfer gate are connected so as to serially transfer the data, and the set data is serially transferred in the connecting state by means of a delayed action resulting from an inter-selector delay time.

Abstract: Methods and apparatus, including computer program products, implementing techniques for receiving a request for access to a memory space of an Advanced Switching device, the memory space including a first memory segment and a second memory segment, determining access permissions for the requested memory space, and processing the access request when an access is determined to be permitted. The techniques include identifying a source of the request as a node configuration packet processor, and denying the access if the node configuration packet processor is requesting access to the second memory segment which is assigned to a hidden storage device.

Abstract: Apparatus and systems, as well as methods and articles, may operate to monitor a flag bit to indicate an occurrence of at least one of a plurality of operational excursions associated with a peripheral card coupled to a bus controller.

Abstract: A method is provided of managing hardware triggered hotplug operations of one or more input/output (I/O) cards of a computer system. The method comprises receiving hardware triggers, each of which relates to a hotplug operation to be carried out on an I/O card associated with a card slot, placing the hardware triggers in a queue, and processing the queue of hardware triggers. The method further comprises processing one or more of said hardware triggers. This comprises analysing a hardware trigger to determine the card slot to which said hardware trigger relates, and consulting a hotplug operation policy to determine whether hotplug operations are enabled for said card slot. If hotplug operations are not enabled for said card slot, this further comprises ignoring said hardware trigger, and if hotplug operations are enabled for said card slot, this further comprise querying said slot to determine whether it contains a card.

Abstract: A data communication apparatus is provided, which is capable of properly transmitting and receiving data of low speed specifications such as MIDI data even via a transmission line of high speed specifications such as an IEEE 1394 serial bus, and hence capable of properly processing the data. The data communication apparatus transmits data to a data receiving apparatus having a data processing section that processes received data at a predetermined processing speed. Data to be transmitted is generated at a higher speed than the predetermined processing speed. The generated data is output at an output speed adjusted to the predetermined processing speed, and the output data is transmitted at a higher speed than the predetermined processing speed.

Abstract: An interrupt handling technique is provided that may allow for sharing level sensitive interrupts in systems where interrupts are message based, i.e., edge triggered. An interrupt input unit is provided for receiving level sensitive interrupt requests and generating request occurrence signals therefrom. An edge detection unit generates start signals for edge triggered interrupt messages on the basis of the request occurrence signals. An interrupt termination detection unit receives termination signals each indicating that an interrupt routine relating to a previous edge triggered interrupt message has terminated. The interrupt input unit is controlled to output a request occurrence signal in response to a received termination signal if a previously received level sensitive interrupt request is still active. That is, a second edge triggered interrupt message may be generated.

Abstract: A host-daughtercard interface is pin compatible with a legacy interface but redefines a subset of pins to implement a high-bandwidth double data-rate (DDR) bus. By inspecting a cookie on the daughtercard, the host platform determines whether the daughtercard supports the DDR bus or the legacy interface, and then configures the subset of pins to implement the legacy interface or the DDR bus.

Abstract: A spin counter updating system and method for updating spin counters for spin latches in a multiprocessor computing system. The updating system includes main spin counter value storage for storing spin counter data correlated to at least one spin counter value, and a master agent. The master agent includes agent spin counter value storage for storing spin counter data correlated to at least one spin counter value; and a spin counter signal handler, wherein the spin counter signal handler is adapted to read spin counter data from the main spin counter value storage and to store the read spin counter data to the agent spin counter value storage.

Abstract: A portable electronic device equipped with multi-function high speed bus and the relevant method is provided in the invention. The portable electronic device includes a main electronic apparatus for connecting to an expansion device through an expansion pack. The central processing unit (CPU) of the main electronic apparatus is connected to the host controller by a first system bus. The host controller is connected to the expansion pack by a multi-function high speed bus. The first system bus is electrically connected to the CPU and includes P signal lines; the multi-function high speed bus includes Q signal lines, where Q<P. The host controller bridges the signals from P signal lines of the first system bus and the signals from the Q signal lines of the multi-function high speed bus. The host controller receives the signals from the first system bus in M clock cycles and outputs the signals to the multi-function high speed bus in N clock cycles, where N>M.

Abstract: An electronic shelf includes a plurality of system circuit boards including a first system circuit board containing a first central processing unit (CPU) providing decision-making intelligence for end-user services supported by the first system circuit board. An auxiliary circuit board is connected to the first circuit board and provides input and output communications between the CPU and devices external to both the first system circuit board and auxiliary circuit board. The CPU is solely responsible for decision-making intelligence for management control for at least a predetermined number of system circuit boards while also being responsible for the decision-making intelligence for end-user services supported by the first system circuit board.

Abstract: A method and a switch element for buffer utilization in a network are provided. The method includes, receiving plural frames in a first buffer, if the received frames are less than a full size frame and can be accommodated in the first buffer; sending an available buffer signal after the first buffer has been utilized; and receiving a frame after the available buffer signal has been sent. The switch element includes, a port having a state machine that monitors buffer utilization by receiving plural frames in a first buffer. Also, a method for managing a receive queue for a network is provided. The method includes, copying a receive descriptor queue entry from a first location to another location while a processor is performing a critical operation; and freeing the receive queue entry such that the processor can complete the critical operation.

Abstract: An instruction encoding method is provided for communication between devices. Before transmission, each opcode is multiplied by two. Each operand is multiplied by two and incremented by one. Encoded opcodes and operands are sent as rising edges (i.e., voltage transitions) on a single wire connecting transmitting and receiving devices. The receiving device counts the rising edges to form a total. Even totals correspond to opcodes, odd totals correspond to operands.

Abstract: A method and system for wirelessly coupling a computer with a peripheral device. The peripheral device is initially docked to a docking port in the computer. The computer then listens for identifiers from all peripheral devices within range of the computer, including the identifier for the peripheral device that is presently docked with the computer. The computer then instructs the docked peripheral device to stop sending its identifier. By a process of deduction, the computer is able to identify the docked peripheral device. The step of stopping the docked peripheral device from sending the peripheral device's identifier is preferably controlled by monitoring whether the computer is charging a battery in the docked peripheral device. Thus, the docked peripheral device transmits its identifier only when it is charging its battery.

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Abstract: Disclosed herein are a controller device, a communication system and a controlling method for transmitting commands for designating two modes used in a setup comprising a controller device and a plurality of target devices reserved by the controller device, the devices being interconnected by a data bus for transmitting data in a predetermined communication format, one of the two modes allowing the target devices to communicate with one another, the other mode inhibiting the reserved target devices from thus communicating. Also disclosed are a communication system and a controlling method for varying between such two modes a standby time that must elapse before a command can be accepted following a bus reset, one mode permitting communication between the reserved target devices, the other mode inhibiting such intercommunication.

Abstract: An integrated circuit system (70) includes a processor (130) and a system bus (12) with a first complexity coupled to the processor. Apparatus for enabling communication between the processor and one or more devices through the system bus include a first device (90), a second device (80), and a first bus interface (72) coupled to the system bus (12), coupled to the first device (90) through a first bus (92) with a second complexity less than the first complexity and coupled to the second device (80) through a second bus (82) with a third complexity less than the first complexity.

Abstract: Disclosed herein are a controller device, a communication system and a controlling method for transmitting commands for designating two modes used in a setup comprising a controller device and a plurality of target devices reserved by the controller device, the devices being interconnected by a data bus for transmitting data in a predetermined communication format, one of the two modes allowing the target devices to communicate with one another, the other mode inhibiting the reserved target devices from thus communicating. Also disclosed are a communication system and a controlling method for varying between such two modes a standby time that must elapse before a command can be accepted following a bus reset, one mode permitting communication between the reserved target devices, the other mode inhibiting such intercommunication.

Abstract: In a bus arbitration method and bus arbiter which simultaneously considers fairness and priority and enables fairness and priority to be readjusted by a program, that is, by software, arbitration for ownership of a bus connected to a plurality of bus masters comprises grouping the plurality of bus masters into a plurality of groups and arbitrating the frequency of each bus master's ownership of the bus according to the result of the grouping. It is preferable that each of the plurality of groups has a priority different from the priorities of the others, and in arbitrating the frequency of each bus master owning the bus, arbitration of ownership of the bus by bus masters belonging to the same group is performed according to a round-robin method.

Abstract: Systems, methods, apparatuses, and arrangements enable information to be communicated across a link using different types of signaling. For example, a first type of information is communicated across a bus using a first type of signaling while a second type of information is communicated across the bus using a second type of signaling. By way of example but not limitation, in certain implementation(s) a system including a transmitting unit and a receiving unit are connected by a multi-line bus. The transmitting unit transmits data signals over the multi-line bus using differential signaling and transmits control signals over the multi-line bus using single-ended signaling. The receiving unit interprets signals received in a differential signaling format via the multi-line bus as data signals and interprets signals received in a single-ended signaling format via the multi-line bus as control signals.

Abstract: The technique is disclosed for detecting active ports of an electronic device. The electronic device comprises a plurality of ports, including a first port. A determination is automatically performed as to whether an external component is connected to the first port. The first port is identified as an active port in response to a determination that an external component is connected to the first port. If there no external component is connected to the first port, then the first port is identified as an inactive port. The inactive and active ports may then be distinguished and treated differently during subsequent control and/or management of the plurality of ports. According different implementations the first port may be identified as an active port in response to detection of a capacitive, resistive, and/or inductive load connected to the first port. The first port as may also be identified an active port in response to a determination that a current is flowing through the first port.