Abstract: An insulating film comprising an organic silicon material having a C—Si bond and a Si—O bond is used for a semiconductor integrated circuit, and for polishing of its surface, a polishing compound comprising water and particles of at least one specific rare earth compound selected from the group consisting of a rare earth oxide, a rare earth fluoride, a rare earth oxyfluoride, a rare earth oxide except cerium oxide and a composite compound thereof, or a polishing compound having the above composition and further containing cerium oxide particles, is used. It is possible to provide a high quality polished surface which is free from or has reduced defects such as cracks, scratches or film peeling.

Abstract: A bismuth titanium silicon oxide having a pyrochlore phase, a thin film formed of the bismuth titanium silicon oxide, a method for forming the bismuth-titanium-silicon oxide thin film, a capacitor and a transistor for a semiconductor device including the bismuth-titanium-silicon oxide thin film, and an electronic device employing the capacitor and/or the transistor are provided. The bismuth titanium silicon oxide has good dielectric properties and is thermally and chemically stable. The bismuth-titanium-silicon oxide thin film can be effectively used as a dielectric film of a capacitor or as a gate dielectric film of a transistor in a semiconductor device. Various electronic devices having good electrical properties can be manufactured using the capacitor and/or the transistor having the bismuth-titanium-silicon oxide film.

Abstract: A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the spin processing unit to direct the etching solution along a radius of the wafer; adjusting the flow of the etching solution from the nozzle; adjusting the rotational speed of the spin susceptor to control the residence time of the etching solution; and coordinating the rotational speed of the spin susceptor, flow of etching solution and positioning of the nozzle to maximize the removal of material. The process may be utilized to compensate for the bowl-shaped non-uniformities of an STI oxide. These non-uniformities are compensated for and addressed after a CMP process.

Abstract: On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate surface. The covering layer is patterned in a direction which is vertical with respect to the substrate surface by limiting a process quantity of at least one precursor material and/or by temporarily limiting the deposition process, and is formed as a functional layer or mask for subsequent process steps.

Abstract: The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least one concavity. A second mask is formed on the surface of the prepared structure, a second etching process is then performed to remove the second mask on the concavity, and a third etching process is performed subsequently to extend the depth of the concavity into the substrate. To prepare a conductor with high aspect ratio in the substrate, the first mask and the second mask are preferably made of dielectric material or metal. In addition, to prepare a trench with high aspect ratio in a silicon substrate, the first mask and the second mask are preferably made of dielectric material.

Abstract: Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.

Abstract: A capacitor (10) includes a substrate (12) and two metal electrodes (14, 18). A dielectric layer (16) is formed between the electrodes. Preferably, the dielectric layer has a dielectric constant greater than 25 and an adequate conduction band offset with silicon. Exemplary embodiments proposed use the following material systems: HfuTivTawOxNy, HfuTivOxNy, TiuSrvOxNy, TiuAlvOxNy and HfuSrvOxNy (where u, v, w, x, and y are the atomic proportions of the elements in the dielectric stack).

Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.

Abstract: A method for impregnating the pores of a zeolite low-k dielectric layer with a polymer, and forming an interconnect structure therein, thus mechanically strengthening the dielectric layer and preventing metal deposits within the pores.

Abstract: A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask layer having a sacrificial support structure. The SiN mask is removed and then a breakthrough etch is applied to remove an underlying pad oxide layer. A PSG layer defining a width of each of the fins on a sidewall of each of the support structures is deposited on each of the support structures. At least two fins each having a narrow fin pitch of about 0.25 ?m. are formed. The fins provide a seed layer for at least two selective epitaxially raised source and drain regions, wherein each raised source-drain associated with each fin are interconnected thus forming a source pad and a drain pad.

Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to electro-magnetic (EM) radiation, such as EM radiation having a wavelength component less than about 500 nm. The EM source can include a multi-frequency source of radiation. Additionally, the source of radiation is collimated in order to selectively treat regions of a non-planar film.

Abstract: To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multiplayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multiplayer film. A clamping member is provided on the frame to make the multiplayer film project out to eliminate slack in the multiplayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member.

Abstract: An electronic device containing a polythiophene wherein R represents a side chain, m represents the number of R substituents; A is a divalent linkage; x, y and z represent, respectively, the number of Rm substituted thienylenes, unsubstituted thienylenes, and divalent linkages A, respectively, in the monomer segment subject to z being 0 or 1, and n represents the number of repeating monomer segments in the polymer or the degree of polymerization.

Abstract: Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

Abstract: After a fluid film is formed by supplying a material with fluidity to the surface of a substrate formed with a stepped layer, the fluid film is pressed against the substrate by a pressing member having a planar pressing surface so that the surface of the fluid film is planarized. The fluid film is heated in this state and thereby solidified to form a solidified film having a planar surface.

Abstract: An embodiment of the invention is a HDP CVD FSG layer and an HDP CVD SIN layer with more stability (e.g., less free F and less free H). A feature is that the FSG and SIN are formed using a HDP CVD process with a high plasma density between 1E12 and 1E15 ions/cc and more preferably between 1E14 and 1E15 ions/cc. The high bias has sufficient energy to break the F—Si bonds in the FSG. The high bias has sufficient energy to break the H—Si bonds in the silicon nitride. Whereby the FSG layer has less F and the SiN layer has less H that increases the FSG/SiN interface reliability. The embodiments can be used on smooth surfaces (non-gap fill applications).

Abstract: A method and system are described for increasing the tensile stress in thin films formed on a substrate, such as silicon nitride films. The thin film may be a planar film, or a non-planar film, such as a nitride film formed over a NMOS gate. The thin film is exposed to collimated electro-magnetic (EM) radiation to anisotropically expose the film. The EM radiation can have a component having a wavelength less than about 500 nm. The EM source can include a multi-frequency source of radiation.

Abstract: A process and system for processing a thin film sample (e.g., a semiconductor thin film), as well as the thin film structure are provided. In particular, a beam generator can be controlled to emit at least one beam pulse. With this beam pulse, at least one portion of the film sample is irradiated with sufficient intensity to fully melt such section of the sample throughout its thickness, and the beam pulse having a predetermined shape. This portion of the film sample is allowed to resolidify, and the re-solidified at least one portion is composed of a first area and a second area. Upon the re-solidification thereof, the first area includes large grains, and the second area has a region formed through nucleation. The first area surrounds the second area and has a grain structure which is different from a grain structure of the second area. The second area is configured to facilitate thereon an active region of an electronic device.

Abstract: A manufacturing method of a thin film transistor of a liquid crystal display device using 3-mask includes forming a gate electrode over a substrate, consecutively forming a gate insulating layer and an active layer, forming a first photoresist pattern, removing an active layer formed at a source/drain region, ashing the first photoresist pattern to expose a part of an active region, forming a source/drain electrode, forming a passivation layer, forming a second photoresist pattern that exposes a pixel region over the passivation layer; forming a pixel region by using the second photoresist pattern as a mask, side-etching a part of the passivation layer to expose a part of the drain electrode, forming a pixel electrode material over the second photoresist pattern and the pixel region, and simultaneously removing the second photoresist pattern and the pixel electrode material formed thereon to form a pixel electrode.

Abstract: An electronic device containing a polythiophene wherein R represents a side chain, m represents the number of R substituents; A is a divalent linkage; x, y and z represent, respectively, the number of Rm substituted thienylenes, unsubstituted thienylenes, and divalent linkages A, respectively, in the monomer segment subject to z being 0 or 1, and n represents the number of repeating monomer segments in the polymer or the degree of polymerization.