Patents Examined by Colleen E. Rodgers
  • Patent number: 8012847
    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: September 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Robert D. Patraw, M. Ceredig Roberts, Keith R. Cook
  • Patent number: 7700989
    Abstract: Embodiments of a dielectric layer containing a hafnium titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7564120
    Abstract: Electrical structures and devices may be formed and include an organic passivating layer that is chemically bonded to a silicon-containing semiconductor material to improve the electrical properties of electrical devices. In different embodiments, the organic passivating layer may remain within finished devices to reduce dangling bonds, improve carrier lifetimes, decrease surface recombination velocities, increase electronic efficiencies, or the like. In other embodiments, the organic passivating layer may be used as a protective sacrificial layer and reduce contact resistance or reduce resistance of doped regions. The organic passivation layer may be formed without the need for high-temperature processing.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: July 21, 2009
    Assignee: California Institute of Technology
    Inventors: Nathan S. Lewis, William J. Royea
  • Patent number: 7560301
    Abstract: A method of manufacturing a field effect transistor of the present invention includes: applying a coating liquid 20 containing a solvent 13 as well as first and second organic molecules 11 and 12 that have been dissolved in the solvent 13; and forming a first layer and a second layer by removing the solvent 13 contained in the coating liquid 20 that has been applied. The first layer contains the first organic molecules 11 as its main component. The second layer adjoins the first layer and contains the second organic molecules 12 as its main component. The first organic molecules 11 are a semiconductor material or a precursor of a semiconductor material. The second organic molecules 12 are an insulator material or a precursor of an insulator material. The first organic molecules 11 and the second organic molecules 12 are not compatible with each other.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: July 14, 2009
    Assignee: Panasonic Corporation
    Inventor: Tohru Nakagawa
  • Patent number: 7557028
    Abstract: Methods for producing nanostructures, particularly Group III-V semiconductor nanostructures, are provided. The methods include use of novel Group III and/or Group V precursors, novel surfactants, oxide acceptors, high temperature, and/or stable co-products. Related compositions are also described. Methods and compositions for producing Group III inorganic compounds that can be used as precursors for nanostructure synthesis are provided. Methods for increasing the yield of nanostructures from a synthesis reaction by removal of a vaporous by-product are also described.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: July 7, 2009
    Assignee: Nanosys, Inc.
    Inventors: Erik C. Scher, Mihai A. Buretea, William P. Freeman, Joel Gamoras, Baixin Qian, Jeffery A. Whiteford
  • Patent number: 7556986
    Abstract: A method of fabricating a memory card. The method comprises the initial step of providing a leadframe which has a dambar and a plurality of contacts, each of the contacts being attached to the dambar by at least one tie bar. A layer of tape is applied to the leadframe such that the tape the bottom contact surfaces of the contacts, at least portions of the bottom dambar surface of the dambar. Thereafter, the tie bars are removed from the leadframe. At least one semiconductor die is electrically connected to the leadframe, with a body thereafter being formed on the leadframe such that the bottom contact surfaces are exposed in an exterior surface thereof.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: July 7, 2009
    Assignee: Amkor Technology, Inc.
    Inventors: Jeffrey Alan Miks, Curtis Michael Zwenger, Brenda Gogue
  • Patent number: 7553715
    Abstract: A method of crystallizing an amorphous silicon thin film on a substrate includes loading a substrate onto a stage, the substrate having an amorphous silicon thin film thereon and having first and second regions, performing a first crystallization by irradiating a laser beam on the first region of the amorphous silicon thin film, the first region being crystallized by moving the stage by a first distance, and performing a second crystallization by irradiating the laser beam on the second region, the second region being crystallized by moving the stage by a second distance.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: June 30, 2009
    Assignee: LG Display Co., Ltd.
    Inventor: JaeSung You
  • Patent number: 7550852
    Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 23, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: John P Tellkamp, Akira Matsunami
  • Patent number: 7547574
    Abstract: Example embodiments of the present invention for fabricating an organic thin film transistor including a substrate, a gate electrode, a gate insulating layer, metal oxide source/drain electrodes and an organic semiconductor layer wherein the metal oxide source/drain electrodes are surface-treated with a self-assembled monolayer (SAM) forming compound containing a sulfonic acid group. According to example embodiments of the present invention, the surface of the source/drain electrodes may be modified to be more hydrophobic and/or the work function of a metal oxide constituting the source/drain electrodes may be increased to above that of an organic semiconductor material constituting the organic semiconductor layer. Organic thin film transistors fabricated according to one or more example embodiments of the present invention may exhibit higher charge carrier mobility.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: June 16, 2009
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Hyun Jung Park, Sang Yoon Lee, Eun Jeong Jeong, Kook Min Han, Jung Seok Hahn, Tae Woo Lee
  • Patent number: 7545023
    Abstract: A semiconductor transistor includes a substrate, a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, a channel region positioned in the substrate corresponding to the gate, and a source region and a drain region respectively positioned alongside the channel region. The source region and the drain region are mainly made of a first material and a second material, wherein the first material and the second material have a same lattice structure and different spacing. The source region and the drain region each include a main region in which a percentage of the second material is constant, and a peripheral region in which a percentage of the second material is graded.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: June 9, 2009
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Cheng Chien
  • Patent number: 7544987
    Abstract: High dielectric films of mixed transition metal oxides of titanium and tungsten, or titanium and tantalum, are formed by sequential chemical vapor deposition (CVD) of the respective nitrides and annealing in the presence of oxygen to densify and oxidize the nitrides. The resulting film is useful as a capacitative cell and resists oxygen diffusion to the underlying material, has high capacitance and low current leakage.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Jiong-Ping Lu, Ming-Jang Hwang
  • Patent number: 7537981
    Abstract: An isolated semiconductor device and method for producing the isolated semiconductor device in which the device includes a silicon-on-insulator (SOI) device formed on a substrate. A dielectric film is formed on the insulator and covers the SOI device. The dielectric film may be a single film or a multilayer film. The silicon layer of the SOI device may include a channel region and source/drain regions. The SOI device may further include a gate insulator disposed on the channel region of the silicon layer, a gate disposed on the gate insulator and sidewall spacers formed a side surface of the gate. The dielectric film may also be disposed on an edge portion of the silicon layer. The device structure may further include metallization lines connecting through the isolation dielectric to the gate and to the source/drain regions.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 26, 2009
    Assignee: Kabuhsiki Kaisha Toshiba
    Inventor: Yusuke Kohyama
  • Patent number: 7528429
    Abstract: A ferroelectric capacitor includes: a base substrate; a first electrode provided above the base substrate; a ferroelectric layer provided above the first electrode; a conductive film provided on the ferroelectric layer; a sacrificial layer composed of dielectric material provided above the conductive film; and a second electrode provided above the sacrificial layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 5, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Shinichi Fukada
  • Patent number: 7528068
    Abstract: A semiconductor device has through electrodes with property as an electrode and excellent in manufacturing stability. The through electrode composed of a conductive small diameter plug and a conductive large diameter plug is provided on the semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area of a connection plug and its diameter each, and the cross sectional area of the small diameter plug is made smaller than a cross sectional area of the large diameter plug and its diameter each. Further, a projecting portion where the small diameter plug is projected from a silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: May 5, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Koji Soejima, Masaya Kawano
  • Patent number: 7521718
    Abstract: Provided is an organic light emitting display, comprising a substrate; a driving unit formed over the substrate; a planarization layer formed over the driving unit, the planarization layer comprising a normal tapered edge portion; and an emission unit formed over the planarization layer to be electrically connected to the driving unit.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: April 21, 2009
    Assignee: LG Electronics Inc.
    Inventors: Sun Kil Kang, Changnam Kim, Honggyu Kim, Sangkyoon Kim
  • Patent number: 7517724
    Abstract: The present invention provides a dicing/die bonding sheet which can be used as a dicing tape during dicing, enables ready separation of the semiconductor element and the adhesive layer from the pressure-sensitive adhesive layer during pickup, and in which the adhesive layer has satisfactory adhesiveness as a die bonding material. A dicing/die bonding sheet in which the pressure-sensitive adhesive layer comprises a compound (A), containing intramolecular, radiation curable carbon-carbon double bonds with an iodine value of 0.5 to 20, and at least one compound (B) selected from a group consisting of polyisocyanates, melamine-formaldehyde resins, and epoxy resins, and the adhesive layer comprises an epoxy resin (a), a phenolic resin (b) with a hydroxyl equivalent of at least 150 g/eq., an epoxy group-containing acrylic copolymer (c), comprising from 0.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 14, 2009
    Assignees: Hitachi Chemical Company, Ltd., Furukawa Electric Co., Ltd.
    Inventors: Keiichi Hatakeyama, Michio Uruno, Takayuki Matsuzaki, Yasumasa Morishima, Kenji Kita, Shinichi Ishiwata
  • Patent number: 7514709
    Abstract: A low dielectric constant polymer, comprising monomeric units derived from a compound having the general formula I (R1—R2)n—Si—(X1)4-n, wherein each X1 is independently selected from hydrogen and inorganic leaving groups, R2 is an optional group and comprises an alkylene having 1 to 6 carbon atoms or an arylene, R1 is a polycycloalkyl group and n is an integer 1 to 3. The polymer has excellent electrical and mechanical properties.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: April 7, 2009
    Assignee: Silecs Oy
    Inventors: Juha T. Rantala, Jyri Paulasaari, Janne Kylmä
  • Patent number: 7511298
    Abstract: The present invention provides a process for forming a semiconductor film, comprising the steps of applying a semiconductor particle dispersion liquid to a substrate surface by spray coating in such a manner that the atomized droplets of the dispersion liquid discharged from the spray coater have a mean diameter of about 30 ?m or less, and drying the coating to form a porous semiconductor film; and use of the semiconductor film obtained by the process.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: March 31, 2009
    Assignee: Kansai Paint Co., Ltd.
    Inventors: Masahide Kawaraya, Iwao Hayashi
  • Patent number: 7508024
    Abstract: A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: March 24, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Roger W. Lindsay, Lyle Jones
  • Patent number: 7507670
    Abstract: Methods for cleaning silicon surfaces of electrode assemblies by efficiently removing contaminants from the silicon surfaces without discoloring the silicon surfaces using an acidic solution comprising hydrofluoric acid, nitric acid, acetic acid, and balance deionized water.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: March 24, 2009
    Assignee: Lam Research Corporation
    Inventors: Hong Shih, Tuochuan Huang, Chunhong Zhou