Patents Examined by Colleen Matthews
  • Metal base substrate and manufacturing method thereof
    Patent number: 8980028
    Abstract: In a metal base substrate with a low-temperature sintering ceramic layer located on a copper substrate, bonding reliability is increased between the copper substrate and the low-temperature sintering ceramic layer. A raw laminated body is prepared by stacking, on a surface of a copper substrate, a low-temperature sintering ceramic green layer including a low-temperature sintering ceramic material containing about 10 mol % to about 40 mol % of barium in terms of BaO and about 40 mol % to about 80 mol % of silicon in terms of SiO2, and this raw laminated body is subjected to firing at a temperature at which the low-temperature sintering ceramic green layer is sintered. In the thus obtained metal base substrate, a glass layer composed of Cu—Ba—Si based glass with a thickness of about 1 ?m to about 5 ?m is formed between the metal substrate and the low-temperature sintering ceramic layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 17, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoichi Moriya, Tsuyoshi Katsube, Yuki Takemori, Tetsuo Kanamori, Yasutaka Sugimoto, Takahiro Takada
  • Three-dimensional semiconductor devices and methods of fabricating the same
    Patent number: 8981458
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Insulated gate semiconductor device
    Patent number: 8981471
    Abstract: In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region. If the gate lead wiring is disposed along the four edges of a chip, the area of the non-operative region increases. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part. Furthermore, the protection diode is disposed adjacent to the conductor or the gate lead wiring, and a portion of the protection diode is disposed near a gate pad.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Haruyoshi Yagi, Manabu Yajima
  • Organic light emitting diode display and method for manufacturing the same
    Patent number: 8975660
    Abstract: An organic light emitting diode (OLED) display includes: a substrate; an organic light emitting diode formed on the substrate; a first inorganic layer formed on the substrate and covering the organic light emitting diode; an intermediate layer formed on the first inorganic layer and covering an area relatively smaller than the first inorganic layer; and a second inorganic layer formed on the first inorganic layer and the intermediate layer, and contacting the first inorganic layer at an edge thereof while covering a relatively larger area than the intermediate layer. A third inorganic layer may be formed on the second inorganic layer so as to contact the second inorganic layer at an edge thereof. At least one of the first, second and third inorganic layers is formed by an atomic layer deposition (ALD) method.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: March 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Kwang Kim, Sang-Joon Seo, Seung-Hun Kim
  • Methods of forming a passivation layer
    Patent number: 8975110
    Abstract: In a composition of forming a passivation layer, the composition includes about 30 to about 60 percent by weight of a mixed polymer resin formed by blending polyamic acid and polyhydroxy amide, about 3 to about 10 percent by weight of a photoactive compound, about 2 to about 10 percent by weight of a cross-linking agent and an organic solvent. The passivation layer formed by using the composition has superior mechanical and physical properties, in which disadvantages of polyimide and polybenzoxazole are compensated by mixing both materials.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Young Kim, Chang-Ho Lee, Su-Min Park
  • Semiconductor device reducing risks of a wire short-circuit and a wire flow
    Patent number: 8975760
    Abstract: A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 10, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Shori Fujiwara
  • Semiconductor memory device including alignment key structures
    Patent number: 8970050
    Abstract: A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 3, 2015
    Assignee: SK hynix Inc.
    Inventor: Chang Hyun Lee
  • Non-lithographic line pattern formation
    Patent number: 8969213
    Abstract: A metal layer is deposited over an underlying material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation and/or nitridation. A hard mask portion is formed over the metal layer. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. The sequence of a surface pull back of the hard mask portion, trench etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a line pattern having a spacing that is not limited by lithographic minimum dimensions.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chiahsun Tseng, David V. Horak, Chun-chen Yeh, Yunpeng Yin
  • Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof
    Patent number: 8969136
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle pad and a peripheral lead pad with an inner lead pad between the die attach paddle pad and the peripheral lead pad; forming a component side of the lead frame for exposing an upper portion of a peripheral lead under the peripheral lead pad; forming an encapsulation on the lead frame and the upper portion of the peripheral lead; exposing the peripheral lead pad; depositing a conductive shielding layer on the encapsulation connected to the peripheral lead pad; and forming a mounting side of the lead frame for forming a lower portion of the peripheral lead over a peripheral lead contact pad.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 3, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventor: Reza Argenty Pagaila
  • Embedded heat spreader for package with multiple microelectronic elements and face-down connection
    Patent number: 8970028
    Abstract: A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: March 3, 2015
    Assignee: Invensas Corporation
    Inventor: Wael Zohni
  • Flow sensor, method for manufacturing flow sensor and flow sensor module
    Patent number: 8969977
    Abstract: The invention provides a flow sensor structure for sealing the surface of an electric control circuit and a part of a semiconductor device via a manufacturing method capable of preventing occurrence of flash or chip crack when clamping the semiconductor device via a mold. The invention provides a flow sensor structure comprising a semiconductor device having an air flow sensing unit and a diaphragm formed thereto, and a board or a lead frame having an electric control circuit for controlling the semiconductor device disposed thereto, wherein a surface of the electric control circuit and a part of a surface of the semiconductor device is covered with resin while having the air flow sensing unit portion exposed.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 3, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsutomu Kono, Yuuki Okamoto, Takeshi Morino, Keiji Hanzawa
  • Detection device, photodiode array, and method for manufacturing the same
    Patent number: 8969851
    Abstract: The present invention provides an image pickup device used to capture an image of an object by receiving light in a near infrared region reflected from the object. The image pickup device includes semiconductor light-receiving elements each having a light-receiving layer with a band gap wavelength of 1.65 to 3.0 ?m.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroshi Inada, Yasuhiro Iguchi, Youichi Nagai, Hiroki Mori, Kouhei Miura
  • Radiation-emitting component
    Patent number: 8963181
    Abstract: A radiation-emitting component includes a semiconductor layer stack having an active region that emits electromagnetic radiation, and at least one surface of the semiconductor layer stack or of an optical element that transmits the electromagnetic radiation wherein the surface has a normal vector, wherein on the at least one surface of the semiconductor layer stack or of the optical element through which the electromagnetic radiation passes, an antireflection layer is arranged such that, for a predetermined wavelength, it has a minimum reflection at a viewing angle relative to the normal vector of the surface at which an increase in a zonal luminous flux of the electromagnetic radiation has approximately a maximum.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: February 24, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stefan Grötsch, Jan Marfeld, Jörg E. Sorg, Moritz Engl, Steffen Köhler
  • Integrated circuit packaging system with thermal structures and method of manufacture thereof
    Patent number: 8963320
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Wei Chun Ang
  • Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection
    Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Method for fabricating a semiconductor device
    Patent number: 8963205
    Abstract: A transistor of a semiconductor device includes a substrate, a gate over the substrate, a source/drain region formed in the substrate to have a channel region therebetween, and an epitaxial layer formed below the channel region to have a different lattice constant from the substrate. The epitaxial layer having a different lattice constant with a substrate material is formed below the channel region to apply a stress to the channel region. Thus, the mobility of carriers of the transistor increases.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 24, 2015
    Assignee: SK hynix Inc.
    Inventors: Yong-Soo Kim, Jun-Ki Kim, Se-Aug Jang
  • Electronic device and method of manufacturing the same, and semiconductor device and method of manufacturing the same
    Patent number: 8952359
    Abstract: Disclosed herein is an electronic device, including: (A) a control electrode; (B) a first electrode and a second electrode; and (C) an active layer composed of an organic semiconductor material layer provided between the first electrode and the second electrode so as to face the control electrode through an insulating layer, wherein a portion of the insulating layer contacting at least the active layer is composed of a layer obtained by curing a material expressed by the general structural formula (1), (2) or (3):
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: February 10, 2015
    Assignee: Sony Corporation
    Inventors: Toshio Fukuda, Noriyuki Kawashima
  • Light emitting device, light emitting module, and method for manufacturing light emitting device
    Patent number: 8946738
    Abstract: According to one embodiment, a light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a first insulating layer, a p-side interconnect layer, an n-side interconnect layer, and a second insulating layer. The portion of the second p-side interconnect layer has the L-shaped cross section being configured to include a p-side external terminal exposed from the first insulating layer and the second insulating layer at a third surface having a plane orientation different from the first surface and the second surface. The portion of the second n-side interconnect layer has the L-shaped cross section being configured to include an n-side external terminal exposed from the first insulating layer and the second insulating layer at the third surface.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki, Yosuke Akimoto, Kazuhito Higuchi, Susumu Obata
  • Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same
    Patent number: 8946825
    Abstract: During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: David Yen, Sung-Chieh Lin, Kuoyuan (Peter) Hsu
  • Wiring substrate and semiconductor device
    Patent number: 8945336
    Abstract: A wiring substrate includes an adhesive layer, a wiring layer, and a support substrate. The adhesive layer includes a first surface and a second surface that is opposite to the first surface. The wiring layer is formed on the first surface of the adhesive layer. The support substrate is formed on the second surface of the adhesive layer. The wiring layer is partially exposed in a through hole extending through the adhesive layer and the support substrate in a thicknesswise direction. The support substrate is adhered to the adhesive layer in a removable manner.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Atsushi Nakamura, Mitsuyoshi Imai