Abstract: Semiconductor lasers comprise a substrate; an active layer configured to generate transverse magnetic (TM) polarized light under an electrical bias; an upper cladding layer; a lower cladding layer; and a distributed feedback (DFB) grating defined by the interface of a layer of metal and a layer of semiconductor under the layer of metal, the interface periodically corrugated in the longitudinal direction of the laser with a periodicity of ?DFB=m?/(2neff), wherein m>1. The DFB grating is configured such that loss of one or more antisymmetric longitudinal modes of the laser structure via absorption to the DFB grating is sufficiently maximized so as to produce lasing of a symmetric longitudinal mode of the laser with laser emission characterized by a single-lobe beam along each direction defined by the grating diffraction orders corresponding to emission away from the plane of the grating.

Abstract: A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers.

Abstract: Gallium and nitrogen containing optical devices operable as laser diodes are disclosed. The devices include a gallium and nitrogen containing substrate member, which may be semipolar or non-polar. The devices include a chip formed from the gallium and nitrogen substrate member. The chip has a width and a length. The devices have a cavity oriented substantially parallel to the length of the chip, a dimension of less than 120 microns characterizing the width of the chip, and a pair of etched facets configured on the cavity of the chip. The pair of etched facets includes a first facet configured at a first end of the cavity and a second facet configured at a second end of the cavity.

Abstract: A light-emitting device of an embodiment of the present application comprises a substrate; a first semiconductor light-emitting structure formed on the substrate, wherein the first semiconductor light-emitting structure comprises a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and a first active layer formed between the first semiconductor layer and the second semiconductor layer, wherein the first active layer is capable of emitting a first light having a first dominant wavelength; and a first thermal-sensitive layer formed on a path of the first light, wherein the first thermal-sensitive layer comprises a material characteristic which varies with a temperature change.

Abstract: Various embodiments of an apparatus that simultaneously cools and thermally decouples adjacent electrically-driven devices in close proximity are provided. In one aspect, an apparatus comprises a first non-silicon heat sink and a first silicon-based heat sink disposed on the first non-silicon heat sink. The first silicon-based heat sink is configured to receive a first electrically-driven device on a first portion of the first silicon-based heat sink and to receive a second electrically-driven device on a second portion of the first silicon-based heat sink. The first silicon-based heat sink includes a first groove or a first opening between the first portion and the second portion such that a heat conduction path between the first electrically-driven device and the first non-silicon heat sink through the first silicon-based heat sink is shorter than a heat conduction path between the first electrically-driven device and the second electrically-driven device through the first silicon-based heat sink.

Abstract: The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface which faces away from the first surface, and through holes which pass through the first surface and the second surface; a dielectric layer formed on one or more of the first surface and the second surface and formed with grooves around the through holes on a fourth surface of the dielectric layer facing away from a third surface of the dielectric layer which is attached to the semiconductor chip; through-silicon vias filling the through holes; and bumps formed on the through-silicon vias and on portions of the dielectric layer around the through-silicon vias and filling the grooves.

Abstract: An semiconductor device includes a semiconductor substrate; a metal layer arranged above the semiconductor substrate; a first passivation film that contacts at least a portion of one side surface of the metal layer; and a second passivation film that is arranged extending from the first passivation film to the metal layer, and contacts an upper surface of the first passivation film, and contacts at least a portion of an upper surface of the metal layer.

Abstract: A formulation incorporates nanoparticles, particularly quantum dot (QD) nanoparticles, into an optically clear medium (resin) to be used as a phosphor material in lighting and display applications, and as a down converting phosphor material in LEDs (light emitting diodes). The resin is compatible with QDs to allow high performance and stability of QD-based LEDs, lighting and display applications.

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

Abstract: A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

Abstract: A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.

Abstract: A radio frequency (RF) excited laser assembly includes a pair of opposed electrodes defining an inter-electrode gap and a conductive termination bridge in electrical contact with both electrodes. The termination bridge mechanically supports and positions the electrodes relative to each other and provides a termination impedance for an RF voltage applied to the electrodes. A conical spiral inductor includes one or more metals windings, and one or more concentric terminals, such that the conical spiral inductor defines an inter-winding spacing sufficient to mitigate ionization of a gas medium between windings. A radio frequency (RF) feed-through assembly configured to apply an RF voltage to a pair of opposing electrodes such that a conductor is isolated from a metal sleeve position around the conductor by ion sheath discharge barrier.

Abstract: Embodiments of this invention provide a method to fabricate an electrical contact. The method includes providing a substrate of a compound Group III-V semiconductor material having at least one electrically conducting doped region adjacent to a surface of the substrate. The method further includes fabricating the electrical contact to the at least one electrically conducting doped region by depositing a single crystal layer of germanium over the surface of the substrate so as to at least partially overlie the at least one electrically conducting doped region, converting the single crystal layer of germanium into a layer of amorphous germanium by implanting a dopant, forming a metal layer over exposed surfaces of the amorphous germanium layer, and performing a metal-induced crystallization (MIC) process on the amorphous germanium layer having the overlying metal layer to convert the amorphous germanium layer to a crystalline germanium layer and to activate the implanted dopant.

Abstract: In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

Abstract: An optical device includes a gallium nitride substrate member having an m-plane nonpolar crystalline surface region characterized by an orientation of about ?1 degree towards (000-1) and less than about +/?0.3 degrees towards (11-20). The device also has a laser stripe region formed overlying a portion of the m-plane nonpolar crystalline orientation surface region. In a preferred embodiment, the laser stripe region is characterized by a cavity orientation that is substantially parallel to the c-direction, the laser stripe region having a first end and a second end. The device includes a first cleaved c-face facet, which is coated, provided on the first end of the laser stripe region. The device also has a second cleaved c-face facet, which is exposed, provided on the second end of the laser stripe region.

Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.

Abstract: In one embodiment, a method includes depositing a chalcogenide precursor layer onto a substrate, and annealing the precursor layer in the presence of a gaseous phase comprising volatile species, the partial pressure of each volatile species being approximately constant over substantially all of the surface of the precursor layer, the partial pressure of each species being between approximately 0.1 mTorr and 760 Torr, where the presence of the gaseous phase reduces decomposition of volatile species from the precursor layer during annealing.

Abstract: An assembly (10) for providing an assembly output beam comprises a laser assembly (12), a power source (14), and a system controller (16). The power source (14) is electrically coupled to the laser assembly (12). The system controller (16) directs power from the power source (14) to the laser assembly (12). Additionally, the system controller (16) includes a capacitor assembly (22) that is electrically connected to the laser assembly (12), and a current source (20) that directs power from the power source (14) to the capacitor assembly (22) and the laser assembly (12). The power source (14) and the capacitor assembly (22) cooperate to provide power to the laser assembly (12). Further, the capacitor assembly (22) provides pulses of power and the current source (20) directs the pulses of power to the laser assembly (12). Moreover, the current source (20) charges the capacitor assembly (22) in between the pulses of power.