Patents Examined by Connie Yoha
  • Write driver circuit and method for writing to a spin-torque MRAM
    Patent number: 8929132
    Abstract: A write driver for writing to a spin-torque magnetoresistive random access memory (ST-MRAM) minimizes sub-threshold leakage of the unselected (off) word line select transistors in the selected column. An effective metal resistance in the bit line and/or source line is reduced and power supply noise immunity is increased. Write driver bias signals are isolated from global bias signals, and a first voltage is applied at one end of a bit line using one of a first NMOS-follower circuit or a first PMOS-follower circuit. A second voltage is applied at opposite ends of a source line using, respectively, second and third PMOS-follower circuits, or second and third NMOS-follower circuits.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: January 6, 2015
    Assignee: Everspin Technologies, Inc.
    Inventors: Syed M. Alam, Thomas Andre
  • 8T NVSRAM cell and cell operations
    Patent number: 8929136
    Abstract: One or more embodiments of 8T NVSRAM cell are provided for improving NVSRAM memory architecture with reduced cell size as opposed to the prior art of 12T NVSRAM cell. This novel 8T NVSRAM cell uses one step Write operation under either a FN-channel write scheme to increase a paired flash transistor Vt values in positive direction with a desired ?Vt12 ?1V or a FN-edge write scheme to decrease the Vt values in negative direction with a similar desired ?Vt12?1V to write the ?Vt12 into the paired flash transistors within 1-10 ms without requiring a pre-erase step. There is no need of Program-Inhibit Voltage (SBPI) to inhibit non-select flash transistor from programming. In addition, this 8T NVSRAM cell uses DRAM-like charge-sensing scheme to detect the ?V on Q and QB nodes of SRAM in which is coupled and generated from the ?Vt12 stored in MC1 and MC2 flash transistors.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: January 6, 2015
    Inventors: Peter Wung Lee, Hsing-Ya Tsao
  • Layouts for memory and logic circuits in a system-on-chip
    Patent number: 8902625
    Abstract: An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 2, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Joseph Holt, Roy Mader, Brandon Greiner, Scott B. Anderson
  • Nonvolatile memory device, memory system having the same and block managing method, and program and erase methods thereof
    Patent number: 8891300
    Abstract: In one embodiment, the method includes overwriting a memory cell storing m-bit data to store n-bit data, where n is less than or equal to m. The memory cell has one of a first plurality of program states when storing the m-bit data, and the memory cell has one of a second plurality of program states when storing the n-bit data. The second plurality of program states include at least one program state not in the first plurality of program states.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: November 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Jaehong Kim, Jongha Kim, Junjin Kong
  • Apparatus and method for reforming resistive memory cells
    Patent number: 8885388
    Abstract: A memory includes an array of memory cells, a first module and a second module. The first module is configured to compare a first state of a memory cell with a reference. The memory cell is in the array of memory cells. The second module is configured to, subsequent to a read cycle or a write cycle of the memory cell and based on the comparison, reform the memory cell to adjust a difference between the first state and a second state of the memory cell.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: November 11, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Winston Lee, Peter Lee, Runzi Chang
  • Startup circuit detecting stable system clock
    Patent number: 8885438
    Abstract: A startup circuit is disclosed operable to perform a startup operation for an electronic device comprising digital circuitry. The startup circuit comprises a first clock generator operable to generate a first clock comprising a first period, and a second clock generator operable to generate a second clock independent of the first clock. The second clock is operable to clock the digital circuitry and comprises a second period less than the first period. A first counter counts a first number of the second periods over the first period, and the second clock is enabled to clock the digital circuitry in response to the first counter.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 11, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Robert P. Ryan
  • System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements
    Patent number: 8879317
    Abstract: Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the decoding of the first group of storage elements.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: November 4, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Simon Litsyn, Idan Alrod, Eran Sharon
  • Device for storing a frequency and method for storing and reading out a frequency
    Patent number: 8854862
    Abstract: The disclosure relates to a device for storing a frequency, wherein the device comprises (i) a comparator having an input, an output, a supply voltage input, and a supply voltage output, and (ii) a memristor connected between the input and the comparator and the output of the comparator.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 7, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Veronique Krueger, Stefan Noll
  • Magnetic random access memory
    Patent number: 8848437
    Abstract: A magnetic random access memory is configured as a read/write memory and at least a first section of the magnetic random access memory is configured to be converted to a read only memory.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Uwe Hildebrand, Josef Hausner, Matthias Obemeier, Daniel Bergman
  • Method for optimizing refresh rate for DRAM
    Patent number: 8848471
    Abstract: A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michele M. Franceschini, Hillery C. Hunter, Ashish Jagmohan, Charles A. Kilmer, Kyu-hyoun Kim, Luis A. Lastras, Moinuddin K. Qureshi
  • Charge cycling by equalizing and regulating the source, well, and bit line levels during write operations for NAND flash memory: program to verify transition
    Patent number: 8842471
    Abstract: In non-volatile memory devices, a write typically consists of an alternating set of pulse and verify operations. At the end of a pulse, the device must be biased properly for an accurate verify, after which the device is re-biased for the next pulse. The intervals between the pulse and verify phases are considered. For the interval after a pulse, but before establishing the verify conditions, the source, bit line, and, optionally, the well levels can be equalized and then regulated at a desired DC level. After a verify phase, but before applying the biasing the memory for the next pulse, the source and bit line levels can be equalized to a DC level.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: September 23, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Hao Thai Nguyen, Juan Carlos Lee, Seungpil Lee, Masahide Matsumoto, Jongmin Park, Man Lung Mui, Sung-En Wang
  • Automated control of opening and closing of synchronous dynamic random access memory rows
    Patent number: 8842480
    Abstract: An apparatus including a protocol engine and a built-in self test (BIST) engine. The built-in self test (BIST) engine is coupled to the protocol engine. The built-in self test (BIST) engine may be configured to directly control when to open and close rows of a synchronous dynamic random access memory (SDRAM) during double data rate (DDR) operations.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: September 23, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jackson L. Ellis, Shruti Sinha
  • Circuits and methods for measuring circuit elements in an integrated circuit device
    Patent number: 8837230
    Abstract: A memory circuit device having at least one test element interconnecting memory sections can include at least one first switch coupled to a first memory section between a first node within a tested section and an intermediate node, a test switch coupled between the intermediate node and a forced voltage node, and a second switch coupled between the intermediate node and a second node; wherein the forced voltage node is selectively coupled to receive a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: September 16, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Richard S. Roy
  • Non-volatile semiconductor device, and method of operating the same
    Patent number: 8837227
    Abstract: A non-volatile semiconductor device and a method for operating the same are disclosed, where the non-volatile semiconductor device includes a gate dielectric layer, a p-type floating gate, a coupling gate, a first p-type source/drain, a second p-type source/drain, a first contact plug and a second contact plug. The gate dielectric layer is formed on a n-type semiconductor substrate. The p-type floating gate is formed on the gate dielectric layer. The first p-type source/drain and the second p-type source/drain are formed in the n-type semiconductor substrate. The first and second contact plugs are formed on the first and second p-type source/drains respectively. The coupling gate consists essentially of a capacitor dielectric layer and a third contact plug, where the capacitor dielectric layer is formed on the p-type floating gate, and the third contact plug is formed on the capacitor dielectric layer.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: September 16, 2014
    Assignee: National Tsing Hua University
    Inventors: Chrong-Jung Lin, Ya-Chin King
  • Non-volatile semiconductor memory device and readout method thereof
    Patent number: 8824206
    Abstract: A non-volatile semiconductor device includes: memory strings formed by series connection of memory cells respectively connected to word lines, wherein each memory string is connected between a bit line and a source line via first and second select gate transistors; and a control circuit controlling the first and second select gate transistors, such that when voltage of the word line is raised to a predetermined value for data readout from the memory cell, a first status where the first select gate transistor is turned on and the second select gate transistor is turned off and second status where the first select gate transistor is turned off and the second select gate transistor is turned on are generated alternately.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 2, 2014
    Assignee: Powerchip Technology Corporation
    Inventors: Masayuki Oishi, Nobuhiko Ito
  • Operating method for memory device and memory array and operating method for the same
    Patent number: 8824188
    Abstract: An operating method for a memory device and a memory array and an operating method for the same are provided. The operating method for the memory device comprises following steps. A memory device is made being in a set state. A method for making the memory device being in the set state comprises applying a first bias voltage to the memory device. The memory device in the set state is read. A method for reading the memory device in the set state comprises applying a second bias voltage to the memory device. A recovering bias voltage is applied to the memory device. The step for applying the recovering bias voltage is performed after the step for applying the first bias voltage or the step for applying the second bias voltage.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 2, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Min Lee, Yu-Yu Lin, Ming-Hsiu Lee
  • Hot electron injection nanocrystals MOS transistor
    Patent number: 8824210
    Abstract: The disclosure relates to a hot electron injection MOS transistor, comprising source and drain regions formed in a semiconductor substrate, a control gate, and a floating gate comprising electrically conductive nanoparticles. The control gate comprises a first portion arranged at a first distance from the substrate, a second portion arranged at a second distance less than the first distance from the substrate, and an intermediary portion linking the first and the second portions.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: September 2, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Non-volatile memory having 3D array of read/write elements with low current structures and methods thereof
    Patent number: 8817514
    Abstract: A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet electrode in series with the R/W element and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element. The thickness of the sheet electrode is adjusted to obtain a reduced cross-sectional contact in the circuit path from the word line to the bit line. This allows the R/W memory element to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode is formed with little increase in cell size.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: August 26, 2014
    Assignee: SanDisk 3D LLC
    Inventors: George Samachisa, Johann Alsmeier
  • Semiconductor memory device having low power mode and related method of operation
    Patent number: 8817567
    Abstract: A semiconductor memory device has a normal power mode and a low power mode. In the low power mode, a selection circuit assigns one data address to at least two memory cells in the semiconductor memory device, and it reads or writes one unit of data from the at least two memory cells.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwant-Il Kim
  • Parametric tracking to manage read disturbed data
    Patent number: 8811074
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, data are stored in a first location in a memory, and read from the first location a selected number of times. At least one parameter associated with the first location is measured after the data are read the selected number of times. The data are thereafter migrated to a second location in the memory responsive to the measured parameter indicating a presence of read disturbance in the data in the first location.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: August 19, 2014
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, David Scott Seekins, Mark Allen Gaertner