Patents Examined by Connie Yoha
  • Semiconductor device
    Patent number: 9196349
    Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: November 24, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kazutaka Miyano, Hiroki Fujisawa
  • Nonvolatile memory device, a memory system having the same, and a read method thereof, the read method applying a read pass voltage to a selected wordline after a sensing
    Patent number: 9183939
    Abstract: A method of reading a nonvolatile memory device including: applying a read voltage to a selected wordline of the nonvolatile memory device; applying a read pass voltage to unselected wordlines of the nonvolatile memory device; sensing a state of a memory cell connected to the selected wordline; and applying the read pass voltage to the selected wordline after the sensing.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wan Nam, Kitae Park, Hyun-Wook Park, Jae-Kyun Rhee
  • Fine granularity power gating
    Patent number: 9183906
    Abstract: Rows of a memory array are segmented into a predetermined number of word line groups. Each row in a word line group has a word line disposed between parallel power supply lines. Each of the power supply lines in a row of a word line group is shared by an adjacent row in the word line group. A row on a boundary of a word line group has a power supply line shared by a row on a boundary of an adjacent word line group. All power supply lines in a word line group are at a full power voltage in response to one of the rows in the word line group being selected by a word line. Most power supply lines in an adjacent word line group are at a full power voltage. All power supply lines in other word line groups are at a power-gated voltage.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: November 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chad A. Adams, Harold Pilo
  • Method of writing data in non-volatile memory device
    Patent number: 9183944
    Abstract: A method of writing data in a non-volatile memory device includes receiving a program command and a first row address corresponding to a first word line; performing a first partial programming operation with respect to first memory cells coupled to the first word line; performing a second partial programming operation with respect to second memory cells coupled to a second word line adjacent to the first word line; performing a first verification operation by verifying the first partial programming operation; and selectively performing a first additional programming operation with respect to the first memory cells depending on a result of the first verification operation.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: November 10, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Si-Hwan Kim, Sang-Yong Yoon, Kyung-Ryun Kim
  • Apparatuses and methods including memory with top and bottom data lines
    Patent number: 9177614
    Abstract: Some embodiments include apparatuses and methods having a first set of data lines, a second set of data lines, and memory cells located in different levels of the apparatus. In at least one of such embodiments, the memory cells can be arranged in memory cell strings between the first and second set of data lines. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: November 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Memory devices, circuits and methods having data values based on dynamic change in material property
    Patent number: 9177639
    Abstract: A method can include determining a data value stored in a memory element of a memory cell array based on the length of time required to cause a property of the memory element to change. A memory device can include a plurality of elements programmable into at least two different states; and an electrical bias section that applies sense conditions to a selected element; and a sense section configured to distinguish between the two different states according to whether a change in property occurs in the selected element within a predetermined time under the sense conditions.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: November 3, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: John Ross Jameson, Shane Charles Hollmer, Nad Edward Gilbert
  • Circuits and methods for efficient execution of a read or a write operation
    Patent number: 9171591
    Abstract: A system for efficient execution of a read or a write is described. The system includes a memory array including a way. The system further includes a read and compare circuit. The read and compare circuit compares data stored within lower address memory cells of the way with information received from a storage device to generate a result of comparison. Moreover, the read and compare circuit compares data stored within higher address memory cells of the way with the information to generate a result of comparison. The system further includes a merge and multiplex circuit coupled to the read and compare circuit. The merge and multiplex circuit merges the result of comparison generated based on the comparison with the lower address memory cells and the result of comparison generated based on the comparison with the higher address memory cells to create a merged outcome of comparison.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 27, 2015
    Assignee: Oracle International Corporation
    Inventors: Jungyong Lee, Tsunghsun Hsieh, Chienan Lai
  • Resistive memory devices, circuits and methods having read current limiting
    Patent number: 9165648
    Abstract: A memory device, comprising: read circuits coupled to a plurality of memory elements programmable between at least two different resistance states, the read circuits generating output values based on resistance states of selected memory elements in a read operation; and current limit circuits that limit a current flow through each memory element to less than a program threshold current; wherein the program threshold current corresponds to a current that flows through a memory element being programmed to cause its resistance to change to a resistance between that of two different resistance states.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: October 20, 2015
    Assignee: Adesto Technologies Corporation
    Inventor: John Ross Jameson, III
  • Electronic device comprising semiconductor memory using metal electrode and metal compound layer surrounding sidewall of the metal electrode
    Patent number: 9159912
    Abstract: This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode.
    Type: Grant
    Filed: May 10, 2014
    Date of Patent: October 13, 2015
    Assignee: SK hynix Inc.
    Inventors: Min-Suk Lee, Chang-Hyup Shin
  • Data storage device, controller, and operating method of data storage device
    Patent number: 9153332
    Abstract: A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: October 6, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wonseok Lee, Eun-Jin Yun, Youngkug Moon, Seongsik Hwang, Donghyun Sohn
  • Dynamic random access memory for communications systems
    Patent number: 9153310
    Abstract: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: October 6, 2015
    Assignee: MAXLINEAR, INC.
    Inventor: Curtis Ling
  • Memory device having RRAM-based non-volatile storage array
    Patent number: 9153343
    Abstract: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: October 6, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Ting Chu, Yue-Der Chih
  • Flash memory apparatus with voltage boost circuit
    Patent number: 9153327
    Abstract: A flash memory apparatus is provided. The flash memory apparatus includes a plurality of memory cell regions. Each of the memory cell regions includes a plurality of memory cells, a programming voltage control generator and an erase voltage control generator. The memory cells receives a programming control voltage through a control end point for programming operation, and the memory cells receives an erase control voltage through an erase end point for erasing operation. The programming voltage control generator provides the programming control voltage to the memory cells, and the erase voltage control generator provides the erase control voltage to the memory cells.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: October 6, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Wen-Hao Ching, Shih-Chen Wang
  • Method for driving nonvolatile memory element, and nonvolatile memory device having a variable resistance element
    Patent number: 9153319
    Abstract: A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 6, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shunsaku Muraoka, Satoru Mitani, Takeshi Takagi
  • Embedded memory device and memory controller including the same
    Patent number: 9142317
    Abstract: An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data, the e-fuse memory including, a plurality of e-fuse memory cells configured to store the replacement data, and an e-fuse address selector configured to decode an address of the plurality of e-fuse memory cells and to selectively cause data of one or more of the plurality of e-fuse memory cells to be output based on the decoding result.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younggeun Lee, Youngjin Cho, Hyun-Wook Lee, Junghyo Woo
  • Semiconductor memory device and programming method for flash memory for improving reliabilty of insulating layer of memory cell
    Patent number: 9136004
    Abstract: A programming method for suppressing deterioration of an insulating layer in a memory cell is provided. In the programming method for a flash memory of the invention, a cell unit including programming units that have been programmed is electrically isolated from a bit line; a cell unit not including programming units is electrically coupled with the bit line; a programming voltage is applied to selected word lines; and a pass voltage is applied to non-selected word lines. Moreover, during a period of applying the programming voltage, carriers are generated in a P-well, and hot carriers passing through a depletion region and accelerated by an electric field are injected into the memory cell.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: September 15, 2015
    Assignee: Winbond Electronics Corp.
    Inventor: Riichiro Shirota
  • Semiconductor memory devices utilizing randomization and data programming methods thereof
    Patent number: 9136002
    Abstract: A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongkyu Lee, BoGeun Kim
  • Method and apparatus for reforming a memory cell of a memory
    Patent number: 9129678
    Abstract: A memory including a memory cell and first and second modules. The memory cell has first and second states, where the second state is different than the first state. The first module, subsequent to an initial forming of the memory cell and subsequent to a read cycle or a write cycle of the memory cell, determines a first difference between the first state and a first predetermined threshold or a second difference between the first state and the second state. The second module, subsequent to the first module determining the first difference or the second difference, reforms the memory cell to reset and increase the first difference or the second difference. The second module, during the reforming of the memory cell, applies a first voltage to the memory cell. The first voltage is greater than a voltage applied to the memory cell during the read cycle or the write cycle.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: September 8, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Pantas Sutardja, Albert Wu, Winston Lee, Peter Lee, Runzi Chang
  • Nonvolatile semiconductor memory device with a write sequence including a setting and removing operation
    Patent number: 9117522
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided one at each of intersections of a plurality of first lines and a plurality of second lines and each storing data by a data storing state of a filament; and a control circuit configured to execute a write sequence that writes data to the memory cell, the write sequence including: a setting operation that applies a setting pulse having a first polarity to the memory cell; and a removing operation that applies a removing pulse having a second polarity opposite to the first polarity to the memory cell; and the control circuit, during execution of the write sequence, is configured to repeatedly execute the setting operation until the memory cell attains a desired data storing state, and then to execute the removing operation.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 25, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Junya Matsunami
  • Semiconductor memory systems using regression analysis and read methods thereof
    Patent number: 9111626
    Abstract: A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwanghoon Kim, Junjin Kong, Changkyu Seol, Hong Rak Son