Patents Examined by Cory Eskridge
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Patent number: 8686452Abstract: An optoelectronic apparatus includes an optical device with an optical structure including a plurality of optical elements, and a radiation-emitting or radiation-receiving semiconductor chip with a contact structure which includes a plurality of contact elements that make electrical contact with the semiconductor chip and are spaced apart vertically from the optical structure, wherein the contact elements are arranged in interspaces between the optical elements upon a projection of the contact structure into the plane of the optical structure.Type: GrantFiled: June 25, 2009Date of Patent: April 1, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Peter Brick, Julius Muschaweck, Joachim Frank
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Patent number: 8685863Abstract: The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking.Type: GrantFiled: December 20, 2012Date of Patent: April 1, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Bin-Hong Cheng
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Patent number: 8673692Abstract: Disclosed herein is a novel charging controlled RRAM (Resistance Random Access Memory), and various methods of making such a charging controlled RRAM device. In one example, a device disclosed herein includes a first word line structure formed above a substrate, wherein the first word line structure includes a gate electrode and a nano-crystal containing layer of insulating material, a second word line structure formed above the substrate, wherein the second word line structure comprises a gate electrode and a nano-crystal containing layer of insulating material, a first implant region formed in the substrate proximate the first word line structure, wherein the first implant region defines a first bit line, and a second implant region formed in the substrate proximate the second word line structure, wherein the second implant region defines a second bit line.Type: GrantFiled: January 19, 2012Date of Patent: March 18, 2014Assignees: GLOBALFOUNDRIES Singapore PTE Ltd., Nanyang Technological UniversityInventors: Shyue Seng Tan, Tu Pei Chen
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Patent number: 8664022Abstract: A submount for a light emitting diode and a method for fabricating the same are provided. The method includes the following steps: (a) providing a silicon substrate; (b) forming a mask layer on the silicon substrate to expose a part of the silicon substrate; (c) forming a first silicon oxide layer in the part of the silicon substrate which is exposed; and (d) removing the mask layer and the first silicon oxide layer, so as to form a recess in the silicon substrate.Type: GrantFiled: March 5, 2012Date of Patent: March 4, 2014Assignee: Episil Technologies Inc.Inventors: Le-Sheng Yeh, Cheng-I Chien
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Patent number: 8643145Abstract: A semiconductor device including a substrate, an insulation film being embedded into the substrate and having multiple openings, multiple dummy diffusion layers formed in the substrate and located in the openings, multiple resistance elements being formed over the insulation film so as not to overlap the dummy diffusion layers in a plan view in a resistance element forming region and extending in a first direction, and multiple dummy resistance elements being formed over the insulation film and the dummy diffusion layers and extending in the first direction in the resistance element forming region, in which each of the dummy resistance elements overlaps at least two dummy diffusion layers aligning in a second direction perpendicular to the first direction in a plane horizontal to the substrate in a plan view.Type: GrantFiled: March 7, 2012Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventor: Yukio Takahashi
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Patent number: 8637370Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.Type: GrantFiled: January 19, 2012Date of Patent: January 28, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Purakh Raj Verma, Yi Liang, Dong Yemin
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Patent number: 8618649Abstract: A package for at least one semiconductor device and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor device creating first recesses aligned with a plurality of the electrical terminals. A conductive material is printed in the first recesses forming contact members on the semiconductor device. At least one dielectric layer is selectively printed on at least a portion of the package to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals electrically coupled to the electric terminals on the semiconductor device.Type: GrantFiled: May 27, 2010Date of Patent: December 31, 2013Assignee: HSIO Technologies, LLCInventor: James Rathburn
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Patent number: 8617951Abstract: A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved.Type: GrantFiled: March 28, 2008Date of Patent: December 31, 2013Assignee: Renesas Electronics CorporationInventors: Tomokazu Matsuzaki, Makoto Sasaki, Masakuni Shimizu
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Patent number: 8609442Abstract: A coating film (90) is formed by causing vapor deposition particles (91) discharged from a vapor deposition source opening (61) of a vapor deposition source (60) to pass through a space between a plurality of control plates (81) of a control plate unit (80) and a mask opening (71) of a vapor deposition mask in this order and adhere to a substrate, while the substrate (10) is moved relative to the vapor deposition mask (70) in a state in which the substrate (10) and the vapor deposition mask (70) are spaced apart at a fixed interval. A difference in the amount of thermal expansion between the vapor deposition source and the control plate unit is detected and corrected. It is thereby possible to form, at a desired position on a large-sized substrate, the coating film in which edge blur and variations in the edge blur are suppressed.Type: GrantFiled: October 11, 2011Date of Patent: December 17, 2013Assignee: Sharp Kabushiki KaishaInventors: Satoshi Inoue, Shinichi Kawato, Tohru Sonoda
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Patent number: 8599616Abstract: A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell's channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams.Type: GrantFiled: February 2, 2012Date of Patent: December 3, 2013Assignee: Tower Semiconductor Ltd.Inventors: Yakov Roizin, Avi Strum
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Patent number: 8599571Abstract: Memory card (1) includes at least semiconductor chip (3), circuit board (2) with semiconductor chip (3) mounted on main surface (21), having at least rigidity reducing portion (23) formed in main surface (21) or in a linear region of surface (22) opposite to the main surface, and cover portion (71) for covering semiconductor chip (3) on main surface (21) of circuit board (2), wherein circuit board (2) has a plurality of convex regions (201) which flex in a convex shape toward main surface (21) due to rigidity reducing portion (23).Type: GrantFiled: April 18, 2007Date of Patent: December 3, 2013Assignee: Panasonic CorporationInventors: Hidenobu Nishikawa, Daido Komyoji, Atsunobu Iwamoto, Hiroyuki Yamada, Shuichi Takeda, Shigeru Kondou
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Fuse structure having crack stop void, method for forming and programming same, and design structure
Patent number: 8592941Abstract: The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.Type: GrantFiled: July 19, 2010Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Tom C. Lee, Kevin G. Petrunich, David C. Thomas -
Patent number: 8586392Abstract: A manufacturing method of a display device including a gate electrode film, a first electrode film, a second electrode film, and a conductive film connected to the first electrode film and formed of a conductive layer including a first conductive layer and a second conductive layer formed overlapping the first conductive layer. The method includes the steps of forming the first electrode film and the second electrode film, forming the conductive layer such that the conductive layer is connected to the first electrode film and the second electrode film, and forming the conductive film by removing regions other than predetermined regions of the conductive layer, wherein the conductive layer forming step includes the steps of forming the first conductive layer on the respective upper surfaces of the first electrode film and the second electrode film and forming the second conductive layer on the upper surface of the first conductive layer.Type: GrantFiled: January 11, 2011Date of Patent: November 19, 2013Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Jun Gotoh, Eisuke Hatakeyama, Kenji Anjo, Yoshitomo Ogishima
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Patent number: 8587085Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.Type: GrantFiled: November 1, 2011Date of Patent: November 19, 2013Assignee: Renesas Electronics CorporationInventor: Katsuyuki Horita
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Patent number: 8581348Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.Type: GrantFiled: December 13, 2011Date of Patent: November 12, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Mahbub Rashed, Steven Soss, Jongwook Kye, Irene Y. Lin, James Benjamin Gullette, Chinh Nguyen, Jeff Kim, Marc Tarabbia, Yuansheng Ma, Yunfei Deng, Rod Augur, Seung-Hyun Rhee, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 8575691Abstract: A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region.Type: GrantFiled: March 24, 2010Date of Patent: November 5, 2013Assignee: United Microelectronics Corp.Inventors: Tseng-Hsun Liu, Chiu-Ling Lee, Zheng-Hong Chen, Yi-Ming Wang, Ching-Ming Lee
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Patent number: 8558377Abstract: There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.Type: GrantFiled: November 1, 2011Date of Patent: October 15, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Jin O Yoo
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Patent number: 8552476Abstract: A semiconductor layer has a second impurity concentration. First trenches are formed in the semiconductor layer to extend downward from an upper surface of the semiconductor layer. Each of insulation layers is formed along each of the inner walls of the first trenches. Each of conductive layers is formed to bury each of the first trenches via each of the insulation layers, and extends downward from the upper surface of the semiconductor layer to a first position. A first semiconductor diffusion layer reaches a second position from the upper surface of the semiconductor layer, is positioned between the first trenches, and has a third impurity concentration lower than the second impurity concentration. A length from the upper surface of the semiconductor layer to the second position is equal to or less than half a length from the upper surface of the semiconductor layer to the first position.Type: GrantFiled: September 19, 2011Date of Patent: October 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tsuyoshi Ohta, Masatoshi Arai, Miwako Suzuki
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Patent number: 8552537Abstract: A semiconductor device according to an embodiment, includes a dielectric film and an Si semiconductor part. The dielectric film is formed by using one of oxide, nitride and oxynitride. The Si semiconductor part is arranged below the dielectric film, having at least one element of sulfur (S), selenium (Se), and tellurium (Te) present in an interface with the dielectric film, and formed by using silicon (Si).Type: GrantFiled: August 23, 2011Date of Patent: October 8, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Satoshi Itoh, Hideyuki Nishizawa
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Patent number: 8552534Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.Type: GrantFiled: November 1, 2011Date of Patent: October 8, 2013Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima