Abstract: A semiconductor device includes a silicon carbide semiconductor body. A first shielding region of a first conductivity type is connected to a first contact at a first surface of the silicon carbide semiconductor body. A current spread region of a second conductivity type is connected to a second contact at a second surface of the silicon carbide semiconductor body. A doping concentration profile of the current spread region includes peaks along a vertical direction perpendicular to the first surface. A doping concentration of one peak or one peak-group of the peaks is at least 50% higher than a doping concentration of any other peak of the current spread region. A vertical distance between the one peak or the one peak-group of the current spread region and the first surface is larger than a second vertical distance between the first surface and a maximum doping peak of the first shielding region.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, and a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions and a plurality of fourth semiconductor regions formed in the semiconductor substrate. The semiconductor device further includes a plurality of trenches penetrating the second, third and fourth semiconductor regions, a plurality of gate electrodes respectively provided via a plurality of gate insulating films in the trenches, a plurality of fifth semiconductor regions each provided between one of the gate insulating films at the inner wall of one of the trenches, and the third semiconductor region and the fourth semiconductor region through which the one trench penetrates. The semiconductor device further includes first electrodes electrically connected to the second, third and fourth semiconductor regions, and a second electrode provided on a second main surface of the semiconductor substrate.

Abstract: The present disclosure is directed to gate-all-around (GAA) transistor structures with a low level of leakage current and low power consumption. For example, the GAA transistor includes a semiconductor layer with a first source/drain (S/D) epitaxial structure and a second S/D epitaxial structure disposed thereon, where the first and second S/D epitaxial structures are spaced apart by semiconductor nano-sheet layers. The semiconductor structure further includes isolation structures interposed between the semiconductor layer and each of the first and second S/D epitaxial structures. The GAA transistor further includes a gate stack surrounding the semiconductor nano-sheet layers.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

Abstract: A semiconductor device includes a dielectric layer, a conductive layer formed over the dielectric layer, and a reduction sacrificial layer formed between the dielectric layer and the conductive layer, wherein the reduction sacrificial layer includes a first reduction sacrificial material having higher electronegativity than the dielectric layer, and a second reduction sacrificial material having higher electronegativity than the first reduction sacrificial material.

Abstract: A display device includes a plurality of pixel tiles spaced apart from each other, each of the pixel tiles including a substrate and a plurality of light emitting stacked structures disposed on the substrate, in which a distance between two adjacent light emitting stacked structures in the same pixel tile is substantially equal to a shortest distance between two adjacent light emitting stacked structures of different pixel tiles.

Abstract: A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate.

Abstract: A method of producing a silicon wafer includes: a laser mark printing step of printing a laser mark having a plurality of dots on a silicon wafer; an etching step of performing etching on at least a laser-mark printed region in a surface of the silicon wafer; and a polishing step of performing polishing on both surfaces of the silicon wafer having been subjected to the etching step. In the laser mark printing step, each of the plurality of dots is formed by a first step of irradiating a predetermined position on a periphery of the silicon wafer with laser light of a first beam diameter thereby forming a first portion of the dot and a second step of irradiating the predetermined position with laser light of a second beam diameter that is smaller than the first beam diameter thereby forming a second portion of the dot.

Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable further downsizing of device size. The device includes: a first structural body and a second structural body that are layered, the first structural body including a pixel array unit, the second structural body including an input/output circuit unit, and a signal processing circuit; a first through-via, a signal output external terminal, a second through-via, and a signal input external terminal that are arranged below the pixel array, the first through-via penetrating through a semiconductor substrate constituting a part of the second structural body, the second through-via penetrating through the semiconductor substrate; a substrate connected to the signal output external terminal and the signal input external terminal; and a circuit board connected to a first surface of the substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.

Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.

Abstract: A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [?m], h2 [?m], a point Px3, a straight line Lx, an angle ?x, a point Px0, ? [?m], a point Px1, and a radius Rx [?m], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and ? are set, the shape parameters Rx and ?x are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and ?x to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.

Abstract: A stretchable display device comprises a plurality of island substrates where a plurality of pixels is defined and spaced apart from each other; a lower substrate disposed under the plurality of island substrates and including a plurality of grooves; and a plurality of connecting lines electrically connecting a plurality of pads disposed on adjacent island substrates of the plurality of island substrates; and a lower adhesive layer disposed under the plurality of island substrates and the plurality of connecting lines, and overlapping the plurality of island substrates.

Abstract: A semiconductor device includes: an inversion type semiconductor element that includes: a substrate having a first conductivity type or a second conductivity type; a first conductivity type layer formed on the substrate; a second conductivity type region that is formed on the first conductivity type layer; a JFET portion that is formed on the first conductivity type layer, is sandwiched by the second conductivity type region to be placed; a source region that is formed on the second conductivity region; a gate insulation film formed on a channel region that is a part of the second conductivity type region; a gate electrode formed on the gate insulation film; an interlayer insulation film covering the gate electrode and the gate insulation film, and including a contact hole; a source electrode electrically connected to the source region through the contact hole; and a drain electrode formed on a back side of the substrate.

Abstract: Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body.

Abstract: A method of producing a wafer from a hexagonal single-crystal ingot includes the steps of planarizing an end face of the hexagonal single-crystal ingot, forming a peel-off layer in the hexagonal single-crystal ingot by applying a pulsed laser beam whose wavelength is transmittable through the hexagonal single-crystal ingot while positioning a focal point of the pulsed laser beam in the hexagonal single-crystal ingot at a depth corresponding to a thickness of a wafer to be produced from the planarized end face of the hexagonal single-crystal ingot, recording a fabrication history on the planarized end face of the hexagonal single-crystal ingot by applying a pulsed laser beam to the hexagonal single-crystal ingot while positioning a focal point of the last-mentioned pulsed laser beam in a device-free area of the wafer to be produced.

Abstract: Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

Abstract: A fan-out semiconductor package including a redistribution line structure is provided. The fan-out semiconductor package includes a plurality of redistribution line insulating layers and a plurality of redistribution line patterns arranged on at least one of an upper surface and a lower surface of each of the plurality of redistribution line insulating layers; at least one semiconductor chip arranged on the redistribution line structure and occupying a footprint having a horizontal width that is less than a horizontal width of the redistribution line structure; and a molding member surrounding the at least one semiconductor chip on the redistribution line structure and having a horizontal width that is greater than the horizontal width of the redistribution line structure, wherein the plurality of redistribution line insulating layers have a cascade structure.

Abstract: A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.

Abstract: A lead frame includes a die paddle, a plurality of leads, at least one connector and a bonding layer. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle and an outer lead portion opposite to the inner lead portion. The connector is connected to the die paddle and the inner lead portions of the leads. The bonding layer is disposed on a lower surface of the die paddle and a lower surface of each of the outer lead portions.