Abstract: A method, apparatus, and system for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is bonded to a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. The silicon carbide substrate having the doped layer is etched using a photo-electrochemical etching process, wherein a doping level of the doped layer is such that the doped layer is removed and a silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure is formed using the silicon carbide layer and the set of group III nitride layers.

Abstract: The present invention provides an aluminum nitride wafer and a method for making the same. The method includes forming at least one alignment notch in or at least one flat alignment edge on a periphery of the aluminum nitride wafer. The alignment notch and the flat alignment edge can prevent the aluminum nitride wafer from being in a poor state during the semiconductor manufacturing process and makes it possible to position the aluminum nitride wafer precisely so that the fraction defective can be lowered. The aluminum nitride wafer of the present invention has advantages of effective insulation, efficient heat dissipation, and a high dielectric constant, and can be used in semiconductor manufacturing processes, electronic products, and semiconductor equipment.

Abstract: The present disclosure provides a wafer annealing method, including: preparing a wafer, the wafer includes a plurality of regions concentrically disposed on the wafer; heating the plurality of regions, the heating process includes a plurality of heating stages, each of the heating stages has a different heating rate, temperatures of the plurality of regions vary in each of the heating stages; performing heat preservation on the plurality of regions; and cooling the plurality of regions through blowing nitrogen. The wafer annealing method can improve the electrical uniformity of the wafer.

Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.

Abstract: An actuator device includes a support portion, a movable portion, a connection portion which connects the movable portion to the support portion on a second axis, a first wiring which is provided on the connection portion, a second wiring which is provided on the support portion, and an insulation layer which includes a first opening exposing a surface opposite to the support portion in a first connection part located on the support portion in one of the first wiring and the second wiring and covers a corner of the first connection part. The rigidity of a first metal material forming the first wiring is higher than the rigidity of a second metal material forming the second wiring. The other wiring of the first wiring and the second wiring is connected to the surface of the first connection part in the first opening.

Abstract: A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package.

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

Abstract: A micro component structure includes a substrate, a micro component and a fixing structure. The micro component and the fixing structure are disposed on the substrate. The micro component has a spacing from the substrate. The fixing structure includes a first supporting layer and a second supporting layer. The micro component is connected to the substrate through the fixing structure. The first supporting layer is connected to the micro component and located between the second supporting layer and the micro component. A refractive index of the first supporting layer is greater than a refractive index of the second supporting layer.

Abstract: A semiconductor FinFET device includes a first work function layer configured to form a first threshold voltage and a second work function layer is configured to form a second threshold voltage. As the device is on, the channel region is divided laterally into a first portion and a second portion, wherein the first portion is located under the first work function layer, and wherein the second portion is located under the second work function layer. The first and second work function layers are configured such that the second threshold voltage is greater than the first threshold voltage to provide a higher withstanding voltage. The first work function layer comprises TiN, and the second work function layer comprises TiN and TiAl; or the first work function layer contains TiAl, and the second work function layer comprises TiN and TiAl.

Abstract: A multicolor light-emitting element using fluorescence and phosphorescence, which has a small number of manufacturing steps owing to a relatively small number of layers to be formed and is advantageous for practical application can be provided. In addition, a multicolor light-emitting element using fluorescence and phosphorescence, which has favorable emission efficiency is provided. A light-emitting element which includes a light-emitting layer having a stacked-layer structure of a first light-emitting layer exhibiting light emission from a first exciplex and a second light-emitting layer exhibiting phosphorescence is provided.

Abstract: A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.

Abstract: A light-emitting device is configured to emit light in improved accordance with the Rec. 2020 specification. The light emitting device includes a substrate; a first electrode disposed on the substrate between an outer surface of the light emitting device and the substrate; a second electrode disposed between the first electrode and the outer surface; a first emissive layer in electrical contact with the first electrode and the second electrode, wherein the first emissive layer includes quantum dots that emit light when electrically excited, and wherein the first emissive layer is associated with a first peak wavelength, ?1; and a second emissive layer disposed between the first emissive layer and a viewing side of the light emitting device, wherein the second emissive layer is a photoluminescent layer that includes quantum dots that emit light when optically excited, and the second emissive layer is associated with a second peak wavelength, ?2, different from the first peak wavelength.

Abstract: A semiconductor device includes; an active region; an isolation region defining the active region; a barrier layer on the active region; an upper semiconductor layer on the barrier layer; and a gate structure covering an upper surface, a lower surface, and side surfaces of the upper semiconductor layer in a first direction. The first direction is a direction parallel to an upper surface of the active region, and the barrier layer is disposed between the gate structure and the active region.

Abstract: A semiconductor device includes a semiconductor fin and a gate structure above the semiconductor fin. The semiconductor fin includes a bottom portion and a top portion above the bottom portion. The bottom portion and the top portion are made of different materials. The top portion includes a head part and a neck part between the head part and the bottom portion. The neck part has a width less than a width of the head part, and the neck part is in contact with the bottom portion.

Abstract: A semiconductor structure and a method for forming the same are provided.

Abstract: A first transistor and a second transistor are stacked. The first transistor and the second transistor have a gate electrode in common. At least one of semiconductor films used in the first transistor and the second transistor is an oxide semiconductor film. With the use of the oxide semiconductor film as the semiconductor film in the transistor, high field-effect mobility and high-speed operation can be achieved. Since the first transistor and the second transistor are stacked and have the gate electrode in common, the area of a region where the transistors are disposed can be reduced.

Abstract: Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

Abstract: Electromagnetic interference (EMI) shielding structures for use inside an electronic system are provided, which allow access for mold compound or cables by using baffle-like features on the shield's sides and/or top, as well as methods for shielding components from EMI, or for containing EMI. The structures block external RF from sensitive components and reduce EMI emission from internal, RF generating components.

Abstract: The present disclosure relates to a semiconductor image sensor with improved quantum efficiency. The semiconductor image sensor can include a semiconductor layer having a first surface and a second surface opposite of the first surface. An interconnect structure is disposed on the first surface of the semiconductor layer, and radiation-sensing regions are formed in the semiconductor layer. The radiation-sensing regions are configured to sense radiation that enters the semiconductor layer from the second surface and groove structures are formed on the second surface of the semiconductor layer.

Abstract: A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.