Patents Examined by Cuong Nguyen
  • Patent number: 9514937
    Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip
  • Patent number: 9379108
    Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Wen Liu, Chi-Yuan Shih, Li-Chi Yu, Meng-Chun Chang, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 9368537
    Abstract: A silicon carbide transistor used as an ultraviolet light sensor. The light sensor is mounted inside a probe for detecting ultraviolet light generated by combustion inside an engine. The silicon carbide transistor generates a light voltage that is converted to a digital signal. The digital signal is used in a feedback loop for an engine control module for real time engine control in operating environments. The silicon carbide transistor is mounted inside a glow plug sized engine probe mounted in the cylinder head and the probe includes a quartz window allowing ultraviolet light access between the combustion chamber and the silicon carbide transistor so that the silicon carbide transistor can be mounted proximate the combustion chamber but behind the cooling jackets inside the engine head.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: June 14, 2016
    Inventors: James A. Holmes, Matthew Francis
  • Patent number: 9356160
    Abstract: A flat panel sensor and a flat panel detector are provided on the basis of a top-gate TFT structure. The flat panel sensor comprises a base substrate, and a top-gate TFT and a storage capacitor that are formed on the base substrate; the storage capacitor includes a first conductive layer, a second conductive layer disposed in opposition to the first conductive layer, a third conductive layer for output of an electric signal, and a ground line; the first conductive layer is directly connected to a drain electrode and an active layer of the top-gate TFT, the second conductive layer is directly connected to the ground line, and the third conductive layer is connected to the first conductive layer through a via hole.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: May 31, 2016
    Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaokun Li
  • Patent number: 9343114
    Abstract: Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material projections containing repeating components of an array, and with a terminal semiconductor projection of the row comprising a contact location. An electrically conductive line may be along said row, with the line wrapping around an end of said terminal semiconductor projection and bifurcating into two branches that are along opposing sides of the semiconductor material projections. Some of the semiconductor material of the terminal semiconductor projection may be replaced with dielectric material, and then an opening may be extended into the dielectric material. An electrical contact may be formed within the opening and directly against at least one of the branches. Some embodiments include memory arrays.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: May 17, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Richard T. Housley
  • Patent number: 9343699
    Abstract: An organic light-emitting display apparatus including a substrate; a display unit which defines an active area of the substrate and includes a thin film transistor; concave-convex portions protruded from the substrate in an area outside the active area; and an encapsulation layer which encapsulates the display unit. The thin film transistor includes an active layer, a gate insulating layer on the active layer, a gate electrode, a source electrode, a drain electrode, and an interlayer insulating layer between the gate electrode and the source electrode, and between the gate electrode and the drain electrode. The concave-convex portions include portions of the gate insulating layer and the interlayer insulating layer, and the encapsulation layer covers the concave-convex portions.
    Type: Grant
    Filed: April 27, 2014
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Won-Kyu Kwak
  • Patent number: 9343704
    Abstract: An organic light-emitting device includes a substrate, on which a transparent electrode and a further electrode are applied. An organic light-emitting layer is arranged between the electrodes. At least one optical scattering layer is arranged on a side of the transparent electrode facing away from the organic light-emitting layer.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: May 17, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Daniel Steffen Setz, Thilo Reusch, Nina Riegel
  • Patent number: 9331051
    Abstract: A method and device for interconnecting stacked die surfaces with electrically conductive traces is provided that includes bonding, using a first layer of a photoresist compound, a second die (2) on top of a first die (1), heating the first layer above a pyrolyzation point of the photoresist compound, where the photoresist compound transitions to a stable layer, depositing a second layer of the photoresist compound (PR), using lithography, from a top surface of the first die (1) to a top surface of the second die (2), heating the second photoresist compound layer to a liquid state, where the liquid photoresist compound forms a smooth convex bridge between the first die (1) top surface and the second die (2) top surface, and depositing an electrically conductive layer on the smooth convex bridge, where an electrically conductive trace is formed between the first die (1) top surface and the second die (2) top surface.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: May 3, 2016
    Assignee: Technische Universiteit Eindhoven
    Inventors: Pinxiang Duan, Elbertus Smalbrugge, Oded Raz, Harmen Joseph Sebastiaan Dorren
  • Patent number: 9331276
    Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (?fG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: May 3, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Dipankar Pramanik, Milind Weling
  • Patent number: 9331156
    Abstract: To manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor. An oxide semiconductor film is deposited by a sputtering method with the use of a polycrystalline sputtering target. In that case, partial pressure of water in a deposition chamber before or in the deposition is set to be lower than or equal to 10?3 Pa, preferably lower than or equal to 10?4 Pa, more preferably lower than or equal to 10?5 Pa. Thus, a dense oxide semiconductor film is obtained. The density of the oxide semiconductor film is higher than 6.0 g/cm3 and lower than 6.375 g/cm3.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 3, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Yusuke Nonaka, Hiroshi Kanemura
  • Patent number: 9331303
    Abstract: Disclosed herein is an organic light-emitting diode lighting apparatus. The organic light-emitting diode lighting apparatus may include a transparent substrate main body with a plurality of groove lines formed therein, auxiliary electrodes formed in at least of the plurality of groove lines, a first electrode formed on the substrate main body, positive temperature coefficients configured to connect the auxiliary electrodes and the first electrode, an organic emission layer formed on the first electrode, and/or a second electrode formed on the organic emission layer.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 3, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jin-Kwang Kim
  • Patent number: 9324700
    Abstract: A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 9324774
    Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 26, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyunho Kim, Seokwoo Lee, Heedong Choi, Sangjin Lee, Seongmoh Seo
  • Patent number: 9324860
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of the first region is larger than an effective work function of the second region.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryosuke Iijima
  • Patent number: 9312320
    Abstract: An organic light emitting diode (OLED) display and a method for manufacturing the same are provided. The OLED display includes a substrate, an active layer and a capacitor lower electrode positioned on the substrate, a gate insulating layer positioned on the active layer and the capacitor lower electrode, a gate electrode positioned on the gate insulating layer at a location corresponding to the active layer, a capacitor upper electrode positioned on the gate insulating layer at a location corresponding to the capacitor lower electrode, a first electrode positioned to be separated from the gate electrode and the capacitor upper electrode, an interlayer insulating layer positioned on the gate electrode, the capacitor upper electrode, and the first electrode, a source electrode and a drain electrode positioned on the interlayer insulating layer, and a bank layer positioned on the source and drain electrodes.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: April 12, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyunho Kim, Seokwoo Lee, Heedong Choi, Sangjin Lee, Seongmoh Seo
  • Patent number: 9310552
    Abstract: Described embodiments include photonic integrated circuits and systems with photonic devices, including thermal isolation regions for the photonic devices. Methods of fabricating such circuits and systems are also described.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: April 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9312208
    Abstract: A through silicon via structure is disclosed. The through silicon via includes: a substrate; a first dielectric layer disposed on the substrate and having a plurality of first openings, in which a bottom of the plurality of first openings is located lower than an original surface of the substrate; a via hole disposed through the first dielectric layer and the substrate, in which the via hole not overlapping for all of the plurality of first openings; a second dielectric layer disposed within the plurality of first openings and on a sidewall of the via hole while filling the plurality of first openings; and a conductive material layer disposed within the via hole having the second dielectric layer on the sidewall of the via hole, thereby forming a through silicon via.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
  • Patent number: 9305993
    Abstract: A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: April 5, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chen-Yuan Lin, Ching-Lin Chan, Cheng-Chi Lin, Shih-Chin Lien
  • Patent number: 9306031
    Abstract: A compound semiconductor device includes a substrate having an opening formed from the rear side thereof; a compound semiconductor layer disposed over the surface of the substrate; a local p-type region in the compound semiconductor layer, partially exposed at the end of the substrate opening; and a rear electrode made of a conductive material, disposed in the substrate opening so as to be connected to the local p-type region.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 5, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yuichi Minoura
  • Patent number: 9299864
    Abstract: Various embodiments of a novel structure of a Ge/Si avalanche photodiode with an integrated heater, as well as a fabrication method thereof, are provided. In one aspect, a doped region is formed either on the top silicon layer or the silicon substrate layer to function as a resistor. When the environmental temperature decreases to a certain point, a temperature control loop will be automatically triggered and a proper bias is applied along the heater, thus the temperature of the junction region of a Ge/Si avalanche photodiode is kept within an optimized range to maintain high sensitivity of the avalanche photodiode and low bit-error rate level.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: March 29, 2016
    Assignee: SiFotonics Technologies Co., Ltd.
    Inventors: Tuo Shi, Pengfei Cai, Liangbo Wang, Nai Zhang, Wang Chen, Su Li, Ching-yin Hong, Mengyuan Huang, Dong Pan