Abstract: Methods and apparatuses are provided in connection with a transparent electrode on organic photovoltaic cells. A layer of dissolvable material is formed on a substrate. A solution having conductive nanowires suspended therein is deposited on the layer of dissolvable material. The solution is evaporated to form a nanowire mesh. The nanowire mesh is heated to sinter junctions between nanowires in the nanowire mesh. The nanowire mesh is affixed on a layer of one or more organic photovoltaic cells. The layer of dissolvable material is dissolved to deposit the nanowire mesh on the layer of one or more organic photovoltaic cells.

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

Abstract: Disclosed herein is a light emitting module. The light emitting module according to an exemplary embodiment includes a circuit board which has a cavity and includes a metal board, an insulation layer, and a circuit pattern, an insulation board disposed in the cavity, at least one light emitting device disposed on the insulation board, first and second pads disposed on the insulation board to be electrically connected with the light emitting device, and a conductive pad for electrically connecting the second pad and the circuit pattern.

Abstract: A power semiconductor device includes a semiconductor substrate, an active device region disposed in the semiconductor substrate, an edge termination region spaced laterally outward from the active device region in the semiconductor substrate, and first and second trenches. The first trench is disposed in the edge termination region and has an inner sidewall, an outer sidewall and a bottom, the inner sidewall being spaced closer to the active device region than the outer sidewall. The second trench is spaced laterally outward from the first trench in the edge termination region, and extends further into the semiconductor substrate than the first trench and has a sidewall which outwardly faces the outer sidewall of the first trench and is doped opposite as the inner sidewall and bottom of the first trench.

Abstract: An integrated multi-axis mechanical device and integrated circuit system. The integrated system can include a silicon substrate layer, a CMOS device region, four or more mechanical devices, and a wafer level packaging (WLP) layer. The CMOS layer can form an interface region, on which any number of CMOS and mechanical devices can be configured. The mechanical devices can include MEMS devices configured for multiple axes or for at least a first direction. The CMOS layer can be deposited on the silicon substrate and can include any number of metal layers and can be provided on any type of design rule. The integrated MEMS devices can include, but not exclusively, any combination of the following types of sensors: magnetic, pressure, humidity, temperature, chemical, biological, or inertial. Furthermore, the overlying WLP layer can be configured to hermetically seal any number of these integrated devices.

Abstract: A light emitting diode (LED) includes a base, an LED die grown on the base, a transparent electrically conductive layer formed on a side of the LED die, a protecting layer covering the transparent electrically conductive layer, and a phosphor layer formed on the protecting layer. Through holes extend through the phosphor layer and the protecting layer to make part of light emitted from the LED die directly traveling out from the through holes to illuminate. A method for manufacturing the LED is also provided.

Abstract: An organic light emitting device is provided that includes a substrate; an embossing layer provided on the substrate; a planarization layer provided on the embossing layer; a first electrode provided on the planarization layer; an organic light emitting layer provided on the first electrode; and a second electrode provided on the organic light emitting layer. The planarization layer may include a first planarization layer provided on the embossing layer; and a second planarization layer provided on the first planarization layer. The embossing layer may have a refractive index ranging from about 1.3 to about 1.5. The planarization layer may include a first planarization layer having a surface roughness of about 10 nm to about 50 nm and a refractive index that ranges from about 1.8 to about 2.5; and a second planarization layer provided on the first planarization layer and having a surface roughness of less than about 10 nm.

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One intermediate semiconductor device includes, for instance: a substrate with at least one fin with at least one channel; at least one gate over the channel; at least one hard-mask over the gate; and at least one spacer disposed over the gate and hard-mask. One method includes, for instance: obtaining an intermediate semiconductor device; forming at least one recess into the substrate, the recess including a bottom and at least one sidewall exposing a portion of the at least one fin; depositing a dielectric layer into the at least one recess; removing at least a portion of the dielectric layer to form a barrier dielectric layer; and performing selective epitaxial growth in the at least one recess over the barrier dielectric layer.

Abstract: The proposed illuminator relates to white-light lamps based on LEDs with remote photoluminescent converters. The illuminator comprises a heat removing base with a radiation output orifice, and the LEDs secured near the periphery of the orifice, with, arranged in series at a distance from the a concave photoluminescent converter layer and a concave light reflector, wherein the converter layer's and light reflector's concavities are oriented towards the LED's and the opening. White light mix of the LEDs' and converter layer's radiation exits via the orifice. The converter layer and reflector may have the form of a truncated ellipsoid of revolution, in particular a sphere, or a paraboloid, with a main axis perpendicular to the plane of the orifice, or a cylinder truncated by the plane of the orifice. The outside reflector' surface may have ribbed heat radiators associated with the heat removing base.

Abstract: A semiconductor device includes a semiconductor layer made of a wide bandgap semiconductor and including a gate trench; a gate insulating film formed on the gate trench; and a gate electrode embedded in the gate trench to be opposed to the semiconductor layer through the gate insulating film. The semiconductor layer includes a first conductivity type source region; a second conductivity type body region; a first conductivity type drift region; a second conductivity type first breakdown voltage holding region; a source trench passing through the first conductivity type source region and the second conductivity type body region from the front surface and reaching a drain region; and a second conductivity type second breakdown voltage region selectively formed on an edge portion of the source trench where the sidewall and the bottom wall thereof intersect with each other in a parallel region of the source trench.

Abstract: A light-emitting device comprising: an organic electroluminescence element that has a light-emitting surface and emits light from the light-emitting surface; and a structure layer that is provided directly or indirectly on the light-emitting surface of the organic electroluminescence element, wherein the structure layer has a concavo-convex structure on a surface of the structure layer, the surface being opposite to the organic electroluminescence element, the concavo-convex structure including a first streak array extending in a first direction that is parallel to the surface, a second streak array extending in a second direction that is parallel to the surface and intersects the first direction, and a third streak array extending in a third direction that is parallel to the surface and intersects the first direction and the second direction, the concavo-convex structure includes flat surface portions parallel to the light-emitting surface and an inclined surface portion that is inclined with respect to the

Abstract: In a semiconductor device and a method for manufacturing the same, a pillar pattern is formed in an alternating pattern and a one side contact (OSC) is formed without using a tilted ion implantation process or a mask, resulting in formation of a vertical gate. The semiconductor device includes an alternating or zigzag-type pillar pattern formed over a semiconductor substrate, a first hole formed between pillars of the pillar pattern, a passivation layer formed over a sidewall of the first hole, a second hole formed by partially etching a lower part of the first hole, a bit line formed in the second hole, and a contact formed at a lower part of the pillar pattern.

Abstract: Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN.

Abstract: A MOSFET includes: a substrate having a first trench formed therein, the first trench opening on a side of one main surface; a gate insulating film; and a gate electrode. The substrate includes an n type source region, a p type body region, an n type drift region, and a p type deep region making contact with the body region and extending to a region deeper than the first trench. The first trench is formed such that a distance between the wall surface and the deep region increases with increasing distance from the main surface of the substrate.

Abstract: A schottky barrier diode may include a first n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate, a first p+ region disposed in the first n? type epitaxial layer, a second n type epitaxial layer disposed on the first n? type epitaxial layer and the first p+ region, a second p+ region disposed in the second n type epitaxial layer, a schottky electrode disposed on the second n type epitaxial layer and the second p+ region, and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first p+ region and the second p+ region may be in contact with each other.

Abstract: In a semiconductor device and a method for manufacturing the same, a mesh shaped lower electrode of a peripheral region is used as a reservoir capacitor to increase the size of a region contacting a dielectric film, such that Cs deterioration is minimized. An exemplary semiconductor device may include a line-type storage node contact plug formed over a semiconductor substrate, a mesh shaped lower electrode formed over the storage node contact plug, and a dielectric film and an upper electrode formed over the lower electrode.

Abstract: An arc welder including an integrated monitor is disclosed. The monitor is capable of monitoring variables during a welding process and weighting the variables accordingly, quantifying overall quality of a weld, obtaining and using data indicative of a good weld, improving production and quality control for an automated welding process, teaching proper welding techniques, identifying cost savings for a welding process, and deriving optimal welding settings to be used as pre-sets for different welding processes or applications.

Abstract: A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper.

Abstract: A process for production of a silicon ingot, by which a silicon ingot exhibiting a low resistivity even in the top portion can be produced. The process for the production of a silicon ingot includes withdrawing a silicon seed crystal from a silicon melt to grow a silicon single crystal, with the silicon seed crystal and the silicon melt containing dopants of the same kind. The process includes the dipping step of dipping a silicon seed crystal containing a dopant in a specific concentration in a silicon melt in such a manner that the temperature difference between both falls within the range of 50 to 97K, and the growing step of growing a silicon single crystal withdrawn after the dipping to form a silicon ingot, the growing step being conducted by using a single crystal puller provided with a thermal shield plate for shielding against radiant heat emitted from the silicon melt and controlling the distance between the thermal shield plate and the silicon melt within a specific range.

Abstract: A component can include a substrate having an opening extending between first and second surfaces thereof, and an electrically conductive via having first and second portions. The first portion can include a first layer structure extending within the opening and at least partially along an inner wall of the opening, and a first principal conductor extending within the opening and at least partially overlying the first layer structure. The first portion can be exposed at the first surface and can have a lower surface located between the first and second surfaces. The second portion can include a second layer structure extending within the opening and at least partially along the lower surface of the first portion, and a second principal conductor extending within the opening and at least partially overlying the second layer structure. The second portion can be exposed at the second surface.