Abstract: An improved local synchronization module which uses Frequency-phase adaptive double locked loop (FPADLL) to control a stable controllable oscillator is disclosed. A single physical feedback loop is implemented which can operate in either a phase locked loop mode or a frequency locked loop mode. The sync module includes a controller which determines in which mode the feedback loop operates. The controller also uses slipping information from a network reference recovery interface to reduce slipping. Also effects of ageing of the stable controllable oscillator are predicted and compensated for.

Abstract: A stack position determination circuit in a stackable repeater is disclosed that includes an input connector, an output connector, an initial pin driving circuit, and a pin rotating circuit. The input connector includes a plurality of input connector repeater stack position pins arranged in an hierarchical order so that each input connector repeater stack position pin corresponds to a possible physical position of the repeater in a stack of repeaters. An output connector includes a plurality of output connector repeater stack position pins arranged in an hierarchical order so that each output connector repeater stack position pin corresponds to a possible position of the repeater in a stack of repeaters. An initial pin driving circuit is connected to an initial pin in the input connector repeater stack position pin hierarchical order. The initial pin corresponds to a first position in the stack of repeaters and the initial pin driving circuit is responsive to an initial repeater signal.

Abstract: The invention relates to a method for indicating a multi-slot channel in signalling received over a radio terminal in a TDMA radio system without increasing the amount of signalling compared to normal signalling used for assigning one slot to the channel and for defining the channel in other respects. In the inventive method, an element describing the channel of a normal signalling message is transformed into a code, which identifies the channel as a multi-slot channel and sets the number of successive slots to be included in the multi-slot channel. The element indicating the normal timeslot for the channel is used to indicate the first timeslot to be included in the multi-slot channel.

Abstract: A call fallback scheme is provided in a packet switched network. After receiving incoming calls, a Voice over IP (VoIP) link is established over a packet switched network with a destination endpoint. VoIP packets are generated from the incoming calls and sent over the VoIP link to the destination endpoint. When a low quality of service condition is detected on the VoIP link with the destination endpoint, a fallback call is established with the destination endpoint over a circuit switched network. The VoIP packets for the incoming calls are redirected from the VoIP link to the circuit switched data link. As opposed to simply hairpinning a TDM voice call back over the PSTN network 102, the same VoIP packets for the incoming calls originally destine for the destination endpoint over the packet switched network are rerouted through the fallback call. This simplifies synchronization with VoIP packets sent over the VoIP network.

Abstract: A method and apparatus for packetizing data include processing that begins by determining the bit time occurrence for retrieval of at least one bit of a portion of a data word, which is stored in local memory. Next, the processing determines the status of the data word based on the bit time occurrence for retrieval of the bit. Next, the bit is retrieved from local memory based on the status of the data word. Having retrieved the bit, the status of the data word is updated based on the bit time occurrence of the at least one bit and the data word. Next, the processing applies a data packetizing protocol to the at least one retrieved bit based on the status of the data word to construct a data packet corresponding to the data word.

Abstract: A method and a system for authenticating an electronic financial transaction conducted between a user owning a terminal and a third party via two-way transmissions between the terminal and a cable distribution hub which includes a validation server.

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.

Abstract: A digital communication trunk employing digital discrete multitone communication over twisted pair copper network segments to increase the effective bandwidth therethrough. Each central office includes an end unit to connect to the network segments and digital discrete multitone repeaters are employed throughout the trunk at defined distances to maintain signal quality. A multiplexer can be employed at the central offices to combine multiple baseband signals before transmission and to extract those multiple signals after reception. In one embodiment of the present invention, four T1 rate baseband signals are combined by the multiplexer into a single signal which is transmitted at T2 rates through the trunk.

Abstract: Filtering of network packets is performed. Within a filter controller, a base address for a range of addresses is stored. A second value is also stored which further specifies the range of addresses. When a network packet is received, a network controller extracts a destination address from the network packet. The network controller forwards the destination address to the filter controller. The filter controller compares the destination address to the range of addresses specified by the base address and the second value. The filter controller generates a signal which indicates when the destination address is outside the range of addresses.

Abstract: An Ethernet flow control system, preferably for a Ethernet switch, having flow controlled transmitting ports in compliance with IEEE Standard 802.3x. The flow control system includes a shared resource, a plurality of buffers receiving data frames from the shared resource, and a plurality of transmitting ports. Each transmitting port being associated with one of the plurality of buffers and being flow controllable between an enabled state and a blocked state. The transmitting port removing and transmitting data frames from the associated buffer when in the enabled state. Each transmitting port including a timer for measuring the time that an associated buffer has a data frame and the corresponding transmitting port is in the blocked state. Each port also includes control logic for removing data frames from the associated buffer when the measured time is greater than a predetermined time.

Abstract: In a cell assembling device, an ATM cell assemblage decomposes input signals channel by channel and outputs channel-by-channel signals. At the same time, the cell assemblage generates a write control signal. Further, when one cell of data is written to a buffer, the cell assemblage generates a condition report signal for informing an arbitrating circuit of the channel of the cell. In response, the arbitrating circuit determines a channel to read out on the basis of the amounts of cell data stored in the buffer, and then outputs a read control signal meant for the above channel. On receiving the write control signal, the buffer writes the channel-by-channel signal therein. In response to the read control signal, the buffer outputs the signal of the channel designated by the signal and feeds it to a cell transmission circuit. The transmission circuit adds a cell header to the data output from the buffer to thereby form a cell to be sent.

Abstract: A retiming arrangement for use in a demultiplexer in an SDH data transmission system uses Bit Justification data, and not Pointer data, to modify a recovered clock signal and generate a clock signal for retiming purposes. The invention is especially for use in enabling third party users to carry primary rate timing data across an SDH network.

Abstract: A satellite communication system which performs switching on data cells. A switch (80) receives the data cells at a set of input ports (IP1-IP128) and directs them to a set of output ports (OP1-OP128). In order to arbitrate input data cells contending for the same output port, decision factor codes and routing codes are serially conducted to input registers (210), and a pseudo-random sequence code is appended. The combined codes are ordered by routing code in a decoder (220). The code with the highest decision factor code is selected in one or more determinators (230 and 240). The selected code is identified by a bit in a result register (250).

Abstract: In a router coupled to a number of networks, a data packet is received from a first one of the networks and routed to a second one of the networks. The data packet includes a first portion having a destination network address. The destination network address for the data packet is input to a content addressable memory (“CAM”) while the router is still receiving at least a portion of the data packet, so that the CAM, having network address information stored therein, identifies one of the networks coupled to the router and corresponding to the destination address of the data packet while the router is still receiving at least a portion of the data packet.

Abstract: A Conversion system merges and converts data in a plurality of different data formats from a plurality of different sources, to a selected output data format for transmission on a selected transmission channel. A method for digital data format conversion involves de-packetizing an input packetized datastream. A timing recovery parameter is formed in response to a desired output data format. The depacketized data is re-packetized in response to the desired output data format and the timing recovery parameter is incorporated in the re-packetized data. The re-packetized data is multiplexed in response to the selected format and provided to an output channel.

Abstract: A calendar based ATM cell scheduling device is used to maintain accurate shaping of cell streams in order to satisfy traffic management guarantees. In certain applications cell insertion may occur downstream of the scheduling device, potentially violating traffic descriptors. The correction means provided by the present invention allows for such downstream cell insertion without violating guarantees by generating a calendar slip in the scheduling device.

Abstract: A method for flexible inverse multiplexing for ATM and for link grouping of communication links with different transmission rates and delay. The method of the present invention supports links which use a portion of the link bandwidth for one QoS objective (e.g., low delay) and another portion for another QoS objective (e.g., low cell loss). The method involves servicing each of a number of multiplexed flows with a predetermined number of cells. Cells are assigned to each flow during a number of cycles which make up an ATM frame. The number of cells assigned to each flow during each cycle is dynamically adjusted based upon the requirements of each flow, and may be different for each flow. The number of cells assigned to each flow during each cycle may either be fixed, or may vary from cycle to cycle.

Abstract: An apparatus and method are presented for testing the ability of a pair of serial data transceivers to transmit serial data at one frequency and to receive serial data at another frequency. A serial communication device of the present invention includes a first and second serial data transceivers and a multiplexer formed upon a monolithic semiconductor substrate. Each serial data transceiver includes a receiver and a transmitter which transmits serial data in response to a clock signal. The second serial data transceiver is coupled to receive a reference clock signal. The multiplexer facilitates testing, and is coupled to the first serial data transceiver. The multiplexer receives the reference clock signal, a test clock signal, and a test signal, and provides either the reference clock signal or the test clock signal to the first transceiver dependent upon the test signal. The reference and test clock signals have different frequencies.