Patents Examined by Dale E Page
  • Patent number: 11329024
    Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seok Hong, Jin-woo Park
  • Patent number: 11329028
    Abstract: The present application discloses a semiconductor device with a recessed pad layer and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a second die positioned on the first die, a pad layer positioned in the first die, a filler layer including an upper portion and a recessed portion, and a barrier layer positioned between the second die and the upper portion of the filler layer, between the first die and the upper portion of the filler layer, and between the pad layer and the recessed portion of the filler layer. The upper portion of the filler layer is positioned along the second die and the first die, and the recessed portion of the filler layer is extending from the upper portion and positioned in the pad layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 10, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11328987
    Abstract: A wafer-level packaging based module includes an antenna board and a chip board. The antenna board includes at least one antenna layer with introduced antenna element and a shielding layer with introduced shielding element in the area of the at least one antenna element opposite to the antenna layer. The chip board includes a contacting layer, a rewiring layer opposite to the contacting layer and the shielding layer having at least one shielding element arranged on the rewiring layer. A chip layer having at least one chip is arranged between the contacting layer and the rewiring layer. Further, the chip layer includes at least one via connecting the contacting layer to the rewiring layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 10, 2022
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Ivan Ndip, Tanja Braun, Klaus-Dieter Lang
  • Patent number: 11315873
    Abstract: Techniques for providing vertical integrations of semiconductor chips, magnetic chips, and lead frames. The techniques can include fabricating an integrated circuit (IC) device as a multi-layer IC structure that includes, within a sealed protective enclosure, a first layer including at least one magnetic chip, a second layer including at least one semiconductor chip or die, and a lead frame. The techniques can further include vertically bonding the magnetic chip in the first layer onto the topside of the lead frame, and vertically bonding the semiconductor chip or die in the second layer on top of the magnetic chip to form a multi-layer IC structure.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: April 26, 2022
    Assignee: SUZHOU QING XIN FANG ELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jerry Zhijun Zhai
  • Patent number: 11315898
    Abstract: A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 26, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Klaus Mueller, Andreas Ploessl, Mathias Wendt
  • Patent number: 11315786
    Abstract: The present disclosure provides a semiconductor device structure with fine patterns at different levels and a method for forming the semiconductor device structure, which can prevent the collapse of the fine patterns and reduces the parasitic capacitance between fine patterns The semiconductor device structure includes a substrate; a first target structure disposed over the substrate, wherein the first target structure comprises a first portion, a second portion, and a third portion, a height of the first portion and a height of the second portion are greater than a height of the third portion; a second target structure disposed over the target layer, wherein the second target structure comprises a fourth portion, a fifth portion, and a sixth portion: a low-level conductive pattern positioned between the first target structure and the second target structure; and a high-level conductive pattern positioned in the first target structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Patent number: 11315832
    Abstract: A method for monitoring and controlling a substrate singulation process is described. Device edges are imaged and identified for analysis. Discrepancies in device edges are noted and used to modify a singulation process and to monitor the operation of singulation processes for anomalous behavior.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 26, 2022
    Assignee: Onto Innovation Inc.
    Inventor: Wayne Fitzgerald
  • Patent number: 11316043
    Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 26, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
  • Patent number: 11316109
    Abstract: The present invention discloses a patterned perovskite film, a preparation method thereof, and a display device. The method includes mixing a perovskite precursor and a photo-initiated polymer monomer, and realizing polymerization of a part of a predetermined area under shielding of a photomask, that is, the formed perovskite crystals are encapsulated by the formed polymer with formation of the patterned perovskite film.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 26, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhiping Hu
  • Patent number: 11309429
    Abstract: A thin film transistor includes an active layer over a substrate, a gate electrode over the active layer, a gate line connected with the gate electrode, and a gate insulation film between the active layer and the gate electrode. The active layer includes a channel region overlapping the gate electrode, and a drain region and a source region on respective sides of the channel region. A length of a straight line connecting the drain region and the source region by a shortest distance may be greater than a width of the gate line parallel to the straight line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joonseok Park, Jihun Lim, Myounghwa Kim, Taesang Kim, Yeonkeon Moon
  • Patent number: 11309271
    Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 19, 2022
    Assignee: XINTEC INC.
    Inventors: Jiun-Yen Lai, Chia-Hsiang Chen
  • Patent number: 11296004
    Abstract: A semiconductor package is provided including a first semiconductor package including a first semiconductor chip. The first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor package is disposed on the first semiconductor package. The second semiconductor package includes a second redistribution layer including a redistribution line. A second semiconductor chip is disposed on the second redistribution layer. A thermal pillar is disposed on the second redistribution layer. A heat radiator is disposed on the second semiconductor package and connected to the thermal pillar. The redistribution line is connected to the first semiconductor chip.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Taewon Yoo, Hyunsoo Chung, Myungkee Chung
  • Patent number: 11296043
    Abstract: A semiconductor device package includes a redistribution layer (RDL), a semiconductor device, a transceiver, and a capacitor. The RDL has a first surface and a second surface opposite to the first surface. The semiconductor device is disposed on the first surface of the RDL. The transceiver is disposed on the second surface of the RDL. The capacitor is disposed on the second surface of the RDL. The semiconductor device has a first projected area and the capacitance has a second projected area. The first projected area overlaps with the second projected area.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Chang-Yu Lin
  • Patent number: 11295958
    Abstract: Methods of forming a semiconductor device and semiconductor device formed by the methods are provided. The methods of forming a semiconductor device may include providing a first substrate and a first bonding layer that is provided on the first substrate, forming a sacrificial pattern and an active pattern on a second substrate, forming a second bonding layer on the active pattern, bonding the second bonding layer onto the first bonding layer, removing the second substrate, and removing the sacrificial pattern to expose the active pattern. Forming the sacrificial pattern and the active pattern on the second substrate may include forming a preliminary sacrificial pattern and the active pattern on the second substrate and oxidizing the preliminary sacrificial pattern. The preliminary sacrificial pattern and the active pattern may be sequentially stacked on the second substrate.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: April 5, 2022
    Inventors: Sungmin Kim, Daewon Ha
  • Patent number: 11296050
    Abstract: An electronic assembly, and a method for making the electronic assembly, includes a first electronic component, a second electronic component, and a plurality of interconnects. The plurality of interconnects electrically couple the first electronic component to the second electronic component. Each of the plurality of interconnects comprise one of a plurality of first magnetic components in physical alignment with an associated one of a plurality of second magnetic components, the plurality of second magnetic components being components of one of the second electronic component and the plurality of interconnects.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventor: Rajasekaran Swaminathan
  • Patent number: 11276720
    Abstract: An optical package includes a substrate, an image sensor, a microlens, an optical filter layer, a constraining layer, and a buffer layer. The image sensor is disposed on the substrate. The microlens having a first Young's modulus is disposed on the image sensor. The optical filter layer having a second Young's modulus disposed on the microlens. The constraining layer is disposed between the optical filter layer and the microlens. The buffer layer having a third Young's modulus disposed on the constraining layer. The third Young's modulus is greater than the first Young's modulus and smaller than the second Young's modulus.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 15, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shih-Chieh Tang, Lu-Ming Lai, Chia Yun Hsu
  • Patent number: 11257694
    Abstract: The present disclosure provides a semiconductor device, a method of manufacturing the semiconductor device and a mothed of method of manufacturing a semiconductor device assembly. The semiconductor device includes a substrate, a bonding dielectric disposed on the substrate, a first conductive feature disposed in the bonding dielectric, an air gap disposed in the bonding dielectric to separate a portion of a periphery of the first conductive feature from the bonding dielectric, and a second conductive feature including a base disposed in the bonding dielectric and a protrusion stacked on the base.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: February 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11257741
    Abstract: A semiconductor package may comprise: a first passivation layer forming an electrical connection with one or more first bumps; a substrate layer including a second passivation layer and a silicon layer; a back-end-of-line (BEOL) layer formed on the substrate layer; and a third passivation layer formed on the BEOL layer forming an electrical connection with one or more second bumps, wherein the substrate layer includes a first signal TSV (Through Silicon Via) which transmits a first signal between the BEOL layer and a first lower pad, a second signal TSV which transmits a second signal between the BEOL layer and a second lower pad, and a ground TSV which is disposed between the first signal TSV and the second signal TSV and formed so that one end thereof is connected to the BEOL layer and the other end thereof floats.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo Pu, Jun So Pak, Sung Wook Moon
  • Patent number: 11257689
    Abstract: A 3D semiconductor device, the device comprising: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, and wherein said first level comprises a plurality of trench capacitors.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: February 22, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
  • Patent number: 11251145
    Abstract: A semiconductor substrate has, on an Au electrode pad, an electrolessly-plated Ni film/an electrolessly-plated Pd film/an electrolessly-plated Au film or an electrolessly-plated Ni film/an electrolessly-plated Au film and a method of manufacturing the semiconductor substrate by the steps indicated in (1) to (6) below: (1) a degreasing step; (2) an etching step; (3) a pre-dipping step; (4) a Pd catalyst application step; (5) an electroless Ni plating step; (6) an electroless Pd plating step and electroless Au plating step or an electroless Au plating step.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: February 15, 2022
    Assignee: JX NIPPON MINING & METALS CORPORATION
    Inventors: Takuto Watanabe, Katsuyuki Tsuchida