Abstract: A display device comprises a first electrode of a (1-1)-th subpixel, a first electrode of a (1-2)-th subpixel, a first electrode of a (2-1)-th subpixel, and a first electrode of a (2-2)-th subpixel; a (1-1)-th welding electrode connected to the first electrode of the (1-1)-th subpixel, a (1-2)-th welding electrode connected to the first electrode of the (1-2)-th subpixel, a (2-1)-th welding electrode connected to the first electrode of the (2-1)-th subpixel, and a (2-2)-th welding electrode connected to the first electrode of the (2-2)-th subpixel; and a first repair line overlapping the (1-1)-th welding electrode and the (2-1)-th welding electrode and a second repair line overlapping the (1-2)-th welding electrode and the (2-2)-th welding electrode, wherein the first repair line and the second repair line are disposed on different layers with at least one insulating layer interposed therebetween.

Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.

Abstract: A semiconductor chip includes a chip pad arranged at a surface of the semiconductor chip. A dielectric layer is arranged at the surface of the semiconductor chip. The dielectric layer has an opening within which a contact portion of the chip pad is exposed, the opening having at least one straight side. The dielectric layer includes a solder flux outgassing trench arranged separate from and in the vicinity of the at least one straight side of the opening and that extends laterally beyond sides of the opening adjoining the straight side.

Abstract: Methods, systems, and devices for reduced resistivity for access lines in a memory array are described. A first metal layer may be formed above a via that is configured to couple an access line of a memory array with a corresponding driver. The first metal layer may be oxidized, and then a second metal layer may be formed above the oxidized first metal layer. One or more access lines of the memory device may be formed from the second metal layer, the oxidized first metal layer, or both.

Abstract: Exemplary methods of semiconductor processing may include providing a boron-and-carbon-and-nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include generating a capacitively-coupled plasma of the boron-and-carbon-and-nitrogen-containing precursor. The methods may include forming a boron-and-carbon-and-nitrogen-containing layer on the substrate. The boron-and-carbon-and-nitrogen-containing layer may be characterized by a dielectric constant below or about 3.5.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device is provided. The manufacturing method includes removing a portion of an edge region from a front surface of a first substrate to form a notch in the edge region; bonding the front surface of the first substrate and a front surface of a second substrate together to forma stacked substrate, wherein the stack substrate includes an opening at a position corresponding to the notch; and filling the opening with an embedding member.

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes forming a first protruding structure, a second protruding structure, and a third protruding structure over a substrate. The method also includes performing a depositing process to form a first insulation material layer between the first protruding structure and the second protruding structure. The method further includes performing a first insulation material conversion process onto the first insulation material layer to bend the first protruding structure and the second protruding structure toward opposite directions.

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.

Abstract: The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 ?m, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

Abstract: Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.

Abstract: A device includes a semiconductor chip, a molding compound, an insulating structure, an under-bump-metallurgy (UBM), a conductive ball, and a protection layer. The molding compound laterally surrounds the semiconductor chip. The insulating structure is over the semiconductor chip and the molding compound. The UBM is over the insulating structure and is electrically connected to the semiconductor chip. The conductive ball is in contact with the UBM. The protection layer extends from the UBM to the molding compound.

Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.

Abstract: A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.

Abstract: An electronic component includes a lower insulating layer, an upper insulating layer formed on the lower insulating layer, a first via electrode embedded in the lower insulating layer, a second via electrode embedded in the lower insulating layer at an interval from the first via electrode, and a resistance layer that is made of a metal thin film, is interposed in a region between the lower insulating layer and the upper insulating layer, and is electrically connected to the first via electrode and the second via electrode.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A method of making a semiconductor device includes etching a substrate to define a first trench and a second trench. The method further includes depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs includes a first dielectric layer, and a first conductive layer. The method further includes depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs includes a second dielectric layer, and a second conductive layer. The method further includes planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.