Abstract: The present application discloses a contact structure, a semiconductor device including the contact structure, and a method for fabricating the semiconductor device. The contact structure includes a body portion; and an extending portion downwardly extending from the body portion and comprising a groove. The groove is recessed from a bottom surface of the extending portion, leading towards the body portion, and exposing the body portion.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.

Abstract: A semiconductor apparatus includes a semiconductor element, a control terminal electrically connected to a top electrode of the semiconductor element through a wiring member, and a case member in which at least a portion of the control terminal is embedded and which defines a space for housing the semiconductor element. The control terminal includes a pad to which the wiring member is connected. The case member includes a wiring member positioning part raised on the case member as a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad.

Abstract: In an embodiment, a method includes: forming a gate dielectric layer on a channel region of a semiconductor feature; depositing a work function tuning layer on the gate dielectric layer, the work function tuning layer including a first work function tuning element; depositing a capping layer on the work function tuning layer with atomic layer deposition, the capping layer formed of an oxide or a nitride; performing an anneal process while the capping layer covers the work function tuning layer, the anneal process driving the first work function tuning element from the work function tuning layer into the gate dielectric layer; removing the capping layer to expose the work function tuning layer; and depositing a fill layer on the work function tuning layer.

Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.

Abstract: A semiconductor device includes leads each having an obverse surface facing in a thickness direction and extending in a first direction crossing the thickness direction, a semiconductor element including electrodes connected to the obverse surfaces of the leads, and a sealing resin covering the leads and semiconductor element. The sealing resin includes a resin bottom surface opposite from the semiconductor element with respect to the leads in the thickness direction. The leads are mutually separated in a second direction orthogonal to the thickness direction and the first direction. Each lead includes a first reverse surface, a second reverse surface and a recessed surface facing away from the obverse surface in the thickness direction. The first and the second reverse surfaces are mutually separated with the recessed surface intervening in the first direction and exposed at the resin bottom surface. The recessed surface is covered with the sealing resin.

Abstract: A semiconductor package includes a first semiconductor chip, first and second dummy chips below the first semiconductor chip, a second semiconductor chip between the first and second dummy chips, a first through via penetrating the second semiconductor chip and electrically connected to the first semiconductor chip, second and third through vias penetrating the first and second dummy chips, respectively, and each electrically connected to the first semiconductor chip, a first bonding pad bonding the first semiconductor chip to the second semiconductor chip, a second bonding pad bonding the first semiconductor chip to the first dummy chip, a third bonding pad bonding the first semiconductor chip to the second dummy chip, and a first insulating layer below the second semiconductor chip and below the first and second dummy chips with each of the first, second, and third through vias penetrating the first insulating layer.

Abstract: One or more systems, devices, and/or methods of use provided herein relate to a semiconductor device with separate power supplies for front side and backside stacked power distribution. A semiconductor device can include one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits. The second power supply can be disposed on the first side of the one or more circuits. Further, the third power supply can be disposed on a second side of the one or more circuits. Additionally, the first side of the one or more circuits can be opposite to the second side of the one or more circuits.

Abstract: A package structure includes a circuit substrate, a semiconductor device, a plurality of cooling pins, a cooler lid, an anti-fouling coating and a top lid. The semiconductor device is disposed on and electrically connected to the circuit substrate. The cooling pins are disposed on the semiconductor device. The cooler lid is attached to the cooling pins, wherein the cooler lid includes an inlet opening and an outlet opening exposing portions of the cooling pins. The anti-fouling coating is coated on the cooling pins and on an inner surface of the cooler lid. The top lid is attached to an outer surface of the cooler lid.

Abstract: A semiconductor photoresist composition includes a first organometallic compound, a second organometallic compound, and a solvent. A method of forming patterns utilizing the same is provided.

Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

Abstract: A semiconductor device with a hybrid bonded interface having microfluidic channels is provided. The semiconductor device includes a first die comprising a first passivation layer, wherein the first passivation layer includes one or more first trenches, and a second die comprising a second passivation layer, wherein the second passivation layer includes one or more second trenches. The first die is bonded to the second die via hybrid copper-to-copper bonding, wherein the one or more first trenches and the one or more second trenches form one or more channels.

Abstract: A semiconductor device module includes a device mounted on the surface of an organic substrate; a heat dissipation block bonded and fixed to the surfaces of the device; and a molded resin sealing the device with at least one surface of the heat dissipation block being exposed. The heat dissipation block includes a first portion and a second portion made of materials different in hardness: the first portion is harder than the second portion, and a gradient in hardness from the first portion on the side exposed from the molded resin to the second portion on the side bonded to the device, to keep a good grinding performance of grinding wheel.

Abstract: The present invention provides a chip packaging structure having a heat dissipation plate and a manufacturing method thereof. The packaging structure includes a substrate, at least one chip, the heat dissipation plate, a plastic packaging layer and a metal shielding layer, wherein the heat dissipation plate is bonded to a first surface of the substrate, a thermal interface material is filled between the heat dissipation plate and the chip, the heat dissipation plate is connected to the first surface, and a connection strength between the conductive connector and the substrate and the heat dissipation plate is greater than a connection strength between the thermal interface material and the chip and the heat dissipation plate; the plastic packaging layer exposes at least part of a surface region of the heat dissipation plate; and the metal shielding layer is at least connected to the surface region.

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening in which the first nitride semiconductor layer is exposed in the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface, exposed in the opening, of the first nitride semiconductor layer; removing the second layer using an acidic solution; and after removing the second layer, forming an electrode on the second nitride semiconductor layer. A first etching rate of the first layer for the acidic solution is lower than a second etching rate of the second layer for the acidic solution.

Abstract: A method of bonding first die(s) to a wafer and a die-stack structure includes: providing a first layer of first die(s), each of the first die(s) including a first metal layer; providing the wafer, which includes a second metal layer; bonding the first die(s) to the wafer; forming an insulating layer and a hole, the insulating layer covering the wafer around the first die(s) or filling gap(s) between the first die(s), the hole formed in the insulating layer around the first die(s); forming an interconnect structure in the hole, the first metal layer, the second metal layer and the interconnect structure are electrically connected, thus establishing electrical connection between the first die(s) and the wafer. In this method, it is unnecessary to form TSV within the first die(s), reducing difficulties in the design of internal wiring within the first die(s) and resulting in area savings of the first die(s).

Abstract: A capacitive pressure sensor element. The capacitive pressure sensor element includes a first measuring capacitor, which generates a first sensor signal in a first pressure range, and a second measuring capacitor, which is used as a reference capacitor in the first pressure range and which generates a second pressure-based sensor signal in the second pressure range. A pressure sensor system which has at least two of the pressure sensor elements, and methods for producing the pressure sensor the pressure sensor system are also described.

Abstract: A semiconductor module includes: a semiconductor element; a laminated substrate including a circuit substrate on which the semiconductor element is mounted; a case including a plurality of terminal holes, the case housing the semiconductor element; a plurality of external terminals, each external terminal being inserted into one of two or more terminal holes among the plurality of terminal holes, the plurality of external terminals being electrically connected to the semiconductor element; and a spacer interposed between the laminated substrate and the case. The case and the spacer are bonded to each other by an adhesive. The case includes, for each two adjacent terminal holes among the plurality of terminal holes, a partition between the two adjacent terminal holes. A distance between the first bonding surface and the partition is greater than a thickness of each external terminal.

Abstract: Contact plugs extend along a first axis. Each contact plug includes a second conductor and a first insulator. A first insulator is between the first conductors and the second conductor. A lower face of each contact plug is in contact with an upper face of a unique one of the first conductors. A first one and second one of the contact plugs are adjacent along a second axis that crosses the first axis. A third one of the contact plugs is between the first and second contact plugs on the second axis, and is at a different position from positions of the first and second contact plugs on a third axis orthogonal to the first and second axes.