Abstract: A semiconductor module includes: a semiconductor element; a laminated substrate including a circuit substrate on which the semiconductor element is mounted; a case including a plurality of terminal holes, the case housing the semiconductor element; a plurality of external terminals, each external terminal being inserted into one of two or more terminal holes among the plurality of terminal holes, the plurality of external terminals being electrically connected to the semiconductor element; and a spacer interposed between the laminated substrate and the case. The case and the spacer are bonded to each other by an adhesive. The case includes, for each two adjacent terminal holes among the plurality of terminal holes, a partition between the two adjacent terminal holes. A distance between the first bonding surface and the partition is greater than a thickness of each external terminal.

Abstract: Contact plugs extend along a first axis. Each contact plug includes a second conductor and a first insulator. A first insulator is between the first conductors and the second conductor. A lower face of each contact plug is in contact with an upper face of a unique one of the first conductors. A first one and second one of the contact plugs are adjacent along a second axis that crosses the first axis. A third one of the contact plugs is between the first and second contact plugs on the second axis, and is at a different position from positions of the first and second contact plugs on a third axis orthogonal to the first and second axes.

Abstract: A semiconductor device includes a package substrate, a package component and at least one adhesive pattern. The package component has a thermal interface material (TIM) layer thereon. The adhesive pattern has a first surface facing the package substrate and a second surface opposite to the first surface, and the second surface of the at least one adhesive pattern is substantially coplanar with a surface of the TIM layer.

Abstract: Disclosed is a display device including a display panel that includes a first area and a second area. The second area is divided into a first side area and a second side area around a central axis. The display panel includes a first side normal pixel disposed in each of first and second rows of the first side area, a first side non-normal pixel disposed in the second row among the first and second rows of the first side area, a second side normal pixel disposed in each of first and second rows of the second side area, and a second side non-normal pixel disposed in the first row among the first and second rows of the second side area. Each of the first side non-normal pixel and the second side non-normal pixel further includes a connection wiring connecting a data line and a pixel circuit to each other.

Abstract: A memory stack structure incudes a base die; a bottom memory die stacked over the base die; an intermediate memory die stacked over the bottom memory die; a top memory die stacked over the intermediate memory die; a signal transmission structure electrically connecting the base die, the bottom memory die, the intermediate memory die, and the top memory die to each other; a first power distribution structure electrically connecting the base die to the bottom memory die; and a second power distribution structure electrically connecting the bottom memory die, the intermediate memory die, and the top memory die to each other.

Abstract: A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding material, containing a plurality of spheres embedded in a matrix, is formed on the encapsulant. The shielding material 144 can be formed by spray coating, printing, liquid flow, or droplets. The spheres can have a curved or angled shape, e.g., circular, oval, or many flat or curved surfaces joining as a globe. The spheres each have a shell formed over a core. The shell can be a conductive material, while the core is an insulating material. Alternatively, the shell can be an insulating material, while the core is a conductive material. The shielding material scatters electromagnetic interference noise waves by reflection off the shell of the spheres. The shielding material can absorb electromagnetic interference noise waves into the core of the spheres.

Abstract: The present disclosure provides a semiconductor device and a method for forming the same. The semiconductor device includes a substrate including an isolation structure defining an active region, a gate structure disposed on the active region of the substrate, a source and a drain respectively disposed in the substrate at opposite sides of the gate structure in a first direction, blocking patterns respectively disposed on the source and drain in which each source and drain including first regions covered by the blocking patterns and a second region exposed by the blocking patterns, and first and second silicide layers respectively embedded in the second regions of the source and drain and each including first portions and a second portion between the first portions. A length of the first portion in the first direction is smaller than that of the second portion.

Abstract: A method for manufacturing an SOI wafer including: a step of forming a silicon oxide film by thermal oxidation on an entire surface of a base wafer containing a dopant; and bonding a main surface of a bond wafer to a first main surface via the silicon oxide film, wherein, prior to the thermal oxidation step, a step of forming a CVD insulator film on a second main surface; and a step of forming, on the first main surface, a barrier silicon layer containing a dopant at a lower concentration than a dopant concentration of the base wafer, and in the thermal oxidation step, the barrier silicon layer is thermally oxidized to produce a barrier silicon oxide film, and in the bonding step, the bond wafer is bonded to the base wafer via the barrier silicon oxide film as a part of the silicon oxide film.

Abstract: An integrated circuit (IC) device includes a substrate with a power control circuit, front and back side metal layers, and first and second feed through vias (FTVs). The front side metal layer has first and second front side power rails. The back side metal layer has first and second back side power rails. The first FTV extends through the substrate, and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate, and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails, and is controllable to electrically connect the first front side power rail to the second front side power rail, or electrically disconnect the first front side power rail from the second front side power rail.

Abstract: A film package, includes: a film substrate having first and second surfaces opposing each other; a plurality of wiring patterns respectively including an input pattern, an output pattern, and an interconnection pattern; a first semiconductor chip electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip electrically connected to the interconnection pattern and the output pattern; a protective layer on the first surface to cover at least a portion of the plurality of wiring patterns; a first conductive film on the protective layer and extending in a second direction; and a second conductive film on the second surface to overlap the first conductive film in a third direction.

Abstract: Semiconductor packages including local interconnects and methods of fabrication are described. In an embodiment, a local interconnect is fabricated with one or more cavities filled with a low-k material or air gap where a die-to-die routing path electrically connecting the first die and the second die includes the metal wire spanning across the one or more cavities. In other embodiments fanout can be utilized to create a wider bump pitch for the local interconnect, or for the local interconnect to connect core regions of the dies. Multiple local interconnects can also be utilized to scale down electrostatic discharge.

Abstract: A semiconductor device is extremely reliable because a sealant thereof is difficult to deteriorate even when a SiC semiconductor element is energized. The semiconductor device is produced by sealing a SiC semiconductor element 11 mounted on a multilayer substrate 12 and electrically conductive connection members 14 and 18 with a sealant 20 containing an ultraviolet light absorbent.

Abstract: A flanged stiffener ring for device packages/electronic devices includes flanges protruding from the sides of the stiffener ring body. The flanged stiffener ring is of minimal material to keep weight low, but maintain rigidity and, thus provide stiffening forces to a substrate of the device package to inhibit substrate warpage.

Abstract: A method includes depositing a photoresist layer over a target layer, the photoresist layer comprising an organometallic material; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation; developing the exposed photoresist layer to form a photoresist pattern; forming a spacer on a sidewall of the photoresist pattern; removing the photoresist pattern; after removing the photoresist pattern, patterning the target layer through the spacer.

Abstract: An inspection device is an inspection device that inspects a semiconductor substrate. The inspection device includes a stage, a first ring, and a second ring. A first recess is provided on an upper surface of the stage. The first recess has a ring shape in plan view. The first ring is elastic. The first ring is disposed in the first recess. The second ring presses the first ring in an inward direction of the ring shape so as to press the first ring toward an inner side surface of a side surface of the first recess. The first ring projects toward an upper side further than the upper surface of the stage. In the stage, an exhaust hole is provided. The semiconductor substrate placed on the first ring is vacuum-sucked with exhaustion through the exhaust hole.

Abstract: A memory device can include a semiconductor substrate having a plurality of active semiconductor devices. The memory device can include a plurality of metallization layers disposed over the semiconductor substrate, where each of the plurality of metallization layers is separated from adjacent metallization layers by an interlayer dielectric. The memory device also includes a dummy metal fill disposed in a metallization layer. The dummy metal fill can be connected to a discharge path for dissipating a charge build up in the dummy metal fill to minimize antenna effects. In some embodiments, the discharge path can include the semiconductor substrate, which can be an electrical drain. The antenna protected dummy metal fill ensures is configured such that any accumulated charge during the fabrication process is discharged to the electric drain.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a plurality of dies, a carrier die, and a plurality of channels embedded in the carrier die. The plurality of dies is stacked in the 3D IC. Each of the dies includes circuitry. The carrier die is disposed above the stacked dies in the 3D IC. The carrier die is configured to provide mechanical support to the stacked dies in the 3D IC. The plurality of channels is configured to carry a coolant to cool the 3D IC.

Abstract: A semiconductor package includes a first semiconductor chip including a first main region and a first edge region, and a second semiconductor chip on the first semiconductor chip and including a second main region and a second edge region. The first semiconductor chip includes a first main pad and a first dummy pad respectively on the first main region and the first edge region on a top surface of the first semiconductor chip. The second semiconductor chip includes a first semiconductor substrate, a wiring layer below the first semiconductor substrate and including a wiring dielectric layer and wiring patterns, a second main pad and a second dummy pad respectively on the second main region and the second edge region below the wiring layer. A thickness of the wiring layer is greater on the second main region than on the second edge region.

Abstract: An inertial sensor includes: a substrate; an insulating film provided on a main surface of the substrate; a first semiconductor layer and a second semiconductor layer which are provided on an opposite-side surface of the insulating film from the substrate; a first oxide film provided on a first side surface of the first semiconductor layer on a second semiconductor layer side; a second oxide film provided on a second side surface of the second semiconductor layer on a first semiconductor layer side; a planarization insulating film provided above the first oxide film and the second oxide film and between the first oxide film and the second oxide film; and a wiring provided on the planarization insulating film and electrically coupled to the second semiconductor layer.

Abstract: A method for processing a substrate that includes: forming a passivation layer over sidewalls of a recess in a carbon-containing layer over a substrate by a cyclic passivation process including a plurality of cycles, each of the plurality of cycles including, exposing the substrate to a first gas including a refractory metal in the absence of a plasma, and after exposing to the first gas, exposing the substrate to a second gas including oxygen or nitrogen.