Abstract: Heat from a semiconductor device is effectively dissipated while the height of the semiconductor device is kept low. A semiconductor device includes a cooler configured to cool a semiconductor module. The semiconductor module includes: a metal block, a semiconductor element, a terminal connected to the semiconductor element, and a resin covering a part of the terminal, the metal block, and the semiconductor element. The cooler includes: a metal base including the semiconductor module in a plan view while being in contact with a lower surface of the semiconductor module, and a cooling pipe disposed on an upper surface of the metal base and configured to cool the semiconductor module. The cooling pipe at least partially surrounds the semiconductor module in a plan view.

Abstract: Provided is a cooler that is less likely to cause an uneven degree of cooling during cooling of multiple cooling targets. The cooler is thus provided inside with a flow path of a refrigerant, the flow path including: an outer-peripheral-side header region that is provided on an outer peripheral side of an annular shape and extends in a circumferential direction of the annular shape; an inner-peripheral-side header region that is provided on an inner peripheral side of the annular shape across a separation region from the outer-peripheral-side header region and extends in the circumferential direction; and a fin region serving as the separation region in which a fin is disposed.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes affixing a spacer structure to a bottom side of a plurality of leads of a leadframe. A semiconductor die is attached to a top side of a die pad of the leadframe. The semiconductor die, the leadframe, and the spacer structure are encapsulated with an encapsulant. Portions of the spacer structure and portions of the leads of the plurality of leads are exposed at a bottom side of the encapsulant.

Abstract: A wafer processing method includes an outer edge removing step of removing an outer edge of a first wafer having a first wiring layer formed on a front surface thereof from the front surface, and a polishing step of polishing the first wiring layer on the front surface of the first wafer after the outer edge removing step.

Abstract: Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.

Abstract: A SOI wafer is formed by forming a hole array on a surface of a wafer including a semiconductor material, forming a membrane-cavity structure by annealing process on the wafer, forming a buried oxide layer on an inside of the cavity and an outer oxide layer on an outside of the membrane, and forming a device layer by removing the outer oxide layer.

Abstract: An electronic device is disclosed. The electronic device includes a first interconnection structure, and a first electronic component disposed over the first interconnection structure and having an active surface and a lateral surface. The electronic device also includes a power connection disposed between the first interconnection structure and the active surface of the first electronic component, and a first non-power connection extending along the lateral surface of the first electronic component and electrically connected to the first interconnection structure. The electronic device also includes a second non-power connection disposed between the first interconnection structure and the active surface of the first electronic component. The second non-power connection is configured to block an electromagnetic interference (EMI) between the power connection and the first non-power connection.

Abstract: A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a hard mask on a semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the hard mask covers an exposed surface of the first semiconductor region within the first opening, performing a first selective deposition process to form a contact layer on the exposed surface of the second semiconductor region within the second opening, and performing a second selective deposition process to form a cap layer on the contact layer.

Abstract: A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a via opening is formed through the substrate, where the via opening has an hourglass shaped profile. In an embodiment, a magnetic layer fills the via opening, and a via is through the magnetic layer. In an embodiment, sidewalls of the via are substantially vertical.

Abstract: A printed circuit board includes a substrate body, first, second, and third upper conductive patterns side by side in a first direction on a top surface of the substrate body, and a photosensitive dielectric layer that at least partially covers the top surface of the substrate body. A first trench is in the substrate body between the first and second upper conductive patterns. The first trench has a first surface roughness at a bottom surface thereof. The substrate body has a second surface roughness at the top surface thereof between the second and third upper conductive patterns. The first surface roughness is greater than the second surface roughness. Each of the first and second upper conductive patterns has a first thickness. The third upper conductive pattern has a second thickness greater than the first thickness.

Abstract: A method of preparing a multilayer structure includes providing a single crystal semiconductor handle substrate that includes a front surface, a back surface, a circumferential edge joining the front and back surfaces, and a central plane between the front and back surfaces. The single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 Ohm-cm. The method also includes depositing a semiconductor layer on the front surface of the single crystal semiconductor handle substrate. Depositing the semiconductor layer is performed by two or more cycles of depositing a portion of the semiconductor layer and interrupting the deposition after the portion of the semiconductor layer has been deposited to anneal the portion of the semiconductor layer.

Abstract: An adhesive for a semiconductor, the adhesive containing a thermoplastic resin, a thermosetting resin, a curing agent, and a flux compound having at least one carboxyl group, in which the flux compound has a structure in which an ?-position carbon of the carboxyl group is substituted by at least one electron-withdrawing group.

Abstract: Provided is a display panel. The display panel includes: a base substrate having a display region and a peripheral region surrounding the display region; a plurality of pixel units disposed in the display region and including a light-emitting unit; a barrier structure disposed in the peripheral region and surrounding the plurality of pixel units; a connecting structure disposed in the peripheral region; a first insulating layer disposed between the first electrode layer and the base substrate, wherein a via hole is formed in a portion of the first insulating layer in the peripheral region; a circuit structure disposed in the peripheral region and including a first circuit structure; a second insulating layer disposed on a side of the second metal layer; and a third insulating layer disposed on a side of the second insulating layer and including a body pattern.

Abstract: A semiconductor device has an electrical component and a heat sink disposed over the electrical component. The heat sink has a cover with a wall extending from the cover forming a pocket around a perimeter of the electrical component. The heat sink also has a horizontal step, and a riser extending from the horizontal step to the cover. The wall extends from the cover to form the pocket. A TIM is disposed between the cover and a surface of the electrical component. The TIM can be liquid metal. The heat sink is pressed onto the TIM under force and heat to distribute the TIM between the cover and surface of the electrical component. The TIM remains contained within the pocket by the wall. The wall or cover can have a vent hole. The TIM may extend over a side surface of the electrical component.

Abstract: A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

Abstract: According to the embodiment, a bonded body includes a ceramic substrate, a copper plate. A bonding layer is located on at least one surface of the ceramic substrate. The bonding layer bonds the ceramic substrate and the copper plate. The bonding layer includes a Ti reaction layer including titanium nitride or titanium oxide as a major component, and a plurality of first alloys positioned between the Ti reaction layer and the copper plate. Each of the plurality of first alloys includes at least one selected from a Cu—Sn alloy and a Cu—In alloy. The first alloys have mutually-different Sn concentrations or In concentrations. According to the embodiment, a warp amount can be reduced. A heating rate and a cooling rate in the bonding process can be increased. According to the embodiment, a silicon nitride substrate is favorable for the ceramic substrate.

Abstract: Provided are a display panel and a display device. The display panel includes a display region and a non-display region. The display region includes multiple first power signal lines, and the multiple first power signal lines extend along a first direction. The non-display region includes a power bus and a power lead-out wire. The power bus includes a first bus section and a second bus section, and along the first direction, the first bus section is connected to the power lead-out wire. The display region includes a first display region and a second display region, along the first direction, an overlapping region exists between a projection of the first display region on the power bus and the first bus section, an overlapping region exists between a projection of the second display region on the power bus and the second bus section.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.