Abstract: An image sensor includes a substrate including a pixel array region and a logic region where a surface of the pixel array region is higher than a surface of the logic region, and a light shielding pattern formed over the substrate of the logic region and having a surface on substantially the same plane as a surface of the substrate.

Abstract: An image sensor includes a first pixel having a first color filter, a first reflection region which reflects light from the first color filter, and a first photoelectric conversion portion arranged in a semiconductor layer and located between the first color filter and the first reflection region, and a second pixel including a second color filter, a second reflection region which reflects light from the second color filter, and a second photoelectric conversion portion arranged in the semiconductor layer and located between the second color filter and the second reflection region. Wavelength corresponding to a maximum transmittance of the first color filter is shorter than wavelength corresponding to a maximum transmittance of the second color filter. An area of the first reflection region is smaller than area of the second reflection region.

Abstract: Disclosed is a light emitting diode (LED) package employing a lead terminal with a reflecting surface. The package includes first and second lead terminals that are spaced apart from each other. The first lead terminal has a lower portion with an LED chip mounting area, and at least one reflecting surface formed by being bent from the lower portion. Meanwhile, a package body supports the first and second lead terminals and forms a cavity through which the LED chip mounting area and the reflecting surface of the first lead terminal and a part of the second lead terminal are exposed. The first and second lead terminals extend outside of the package body. Accordingly, light emitted from an LED chip can be reflected on the reflecting surface with high reflectivity, so that the optical efficiency of the package can be improved.

Abstract: A co-integrated HBT/FET apparatus and system, and methods for making the same, are disclosed. A co-integrated HBT/FET apparatus may include a first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a FET device, a separation layer formed over the first epitaxial structure, and a second epitaxial structure formed over the separation layer, the second epitaxial structure forming, at least in part, a heterojunction bipolar transistor (HBT) device.

Abstract: In a thin-film transistor (TFT) substrate, a gate insulating layer is disposed on a gate electrode electrically connected to a gate line. A semiconductor layer is disposed on the gate insulating layer. A source electrode is electrically connected to a data line that intersects the gate line. A drain electrode faces the source electrode and defines a channel area of a semiconductor layer. An organic layer is disposed on the data line and has a first opening exposing the channel area. An inorganic insulating layer is disposed on the organic layer. A pixel electrode is disposed on the inorganic insulating layer and electrically connected to the drain electrode. The inorganic insulating layer covers the first opening, and thickness of the inorganic insulating layer is substantially uniform.

Abstract: According to one embodiment of the present invention, a MOS transistor includes a semiconductor layer including a source region, a drain region, and a channel region disposed between the source region and the drain region. A gate structure is arranged above the channel regions. A source wiring structure is arranged above the source region and is connected to the source region. A drain wiring structure is arranged above the drain region and is connected to the drain region. The width of the source wiring structure is larger than the width of the drain wiring structure, and the height of the source wiring structure is smaller than the height of the drain wiring structure, or vice versa.

Abstract: A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package.

Abstract: A nitride-based light emitting device capable of achieving an enhancement in light emission efficiency and an enhancement in reliability is disclosed. The nitride-based light emitting device includes a light emitting layer including a quantum well layer and a quantum barrier layer, and a stress accommodating layer arranged on at least one surface of the quantum well layer of the light emitting layer.

Abstract: Provided are a reflective electrode and a compound semiconductor light emitting device having the reflective electrode, such as LED or LD is provided. The reflective electrode formed on a p-type compound semiconductor layer of a compound semiconductor light emitting device, comprising a first electrode layer formed one of a Ag and Ag-alloy and forms an ohmic contact with the p-type compound semiconductor layer, a third electrode layer formed of a material selected from the group consisting of Ni, Ni-alloy, Zn, Zn-alloy, Cu, Cu-alloy, Ru, Ir, and Rh on the first electrode layer, and a fourth electrode layer formed of a light reflective material on the third electrode layer.

Abstract: Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process.

Abstract: A submount for a light emitting device package includes a rectangular substrate. A first bond pad and a second bond pad are on a first surface of the substrate. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode thereon. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are a the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. Related LED packages and methods of forming LED packages are disclosed.

Abstract: A III-nitride heterojunction power semiconductor device having a barrier layer that includes a region of reduced nitrogen content.

Abstract: Fabrication of thin-film transistor devices on polymer substrate films that is low-temperature and fully compatible with polymer substrate materials. The process produces micron-sized gate length structures that can be fabricated using inkjet and other standard printing techniques. The process is based on microcrack technology developed for surface conduction emitter configurations for field emission devices.

Abstract: In a light-emitting device and its manufacturing method, mounting by batch process with surface-mount technology, high light extraction efficiency, and low manufacturing cost are realized. The light-emitting device 1 comprises semiconductor layers (2, 3) of p-type and n-type nitride semiconductor, semiconductor-surface-electrodes (21, 31) to apply currents into each of the semiconductor layers (2, 3), an insulating layer 4 which holds the semiconductor layers (2, 3), and mount-surface-electrodes (5). The semiconductor layers (2) has a non-deposited area 20 where the other semiconductor layer (3) is not deposited. The insulating layer (4) has VIA 10 which electrically connect the mount-surface-electrodes 5 and the semiconductor-surface-electrodes (21, 31). In the manufacturing process, firstly.

Abstract: A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

Abstract: A light-emitting device includes a substrate having an epitaxial-forming surface and a back surface opposite to the epitaxial-forming surface, the substrate being formed with a recess indented from the back surface, the back surface having a recessed portion that defines the recess, and a planar portion extending outwardly from the recessed portion; an epitaxy layer; a continuous heat-dissipating layer formed on the planar portion and the recessed portion of the back surface of the substrate; and first and second electrodes coupled electrically to the epitaxy layer.

Abstract: A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench.

Abstract: A semiconductor apparatus is equipped with an internal circuit (201) including a semiconductor element (202)(203) and a protection circuit (101) including a semiconductor (102)(103) for protecting the internal circuit (201) against damage from electrostatic discharge (ESD). The semiconductor elements (102)(103) (202)(203) constituting the internal circuit (201) and the protection circuit (101) include an impurity diffusion region (7)(8) connected by an external terminal and a guard band region (6)(5) formed near the impurity diffusion region (7)(8), respectively. A shortest distance (102L)(103L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (102)(103) of the protection circuit (101) is set to be shorter than a shortest distance (202L)(203L) between the impurity diffusion region (7)(8) and the guard band region (6)(5) in the semiconductor element (202)(203) of the internal circuit (201).

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

Abstract: A GaN crystal substrate is provided, which has a diameter of not less than 20 mm and a thickness of not less than 70 ?m and not more than 450 ?m, and has a light absorption coefficient of not less than 7 cm?1 and not more than 68 cm?1 for light in the wavelength range of not less than 375 nm and not more than 500 nm. A fabricating method of the GaN crystal substrate, and a light-emitting device fabricated using the GaN crystal substrate are also provided.