Abstract: In a light-emitting device and its manufacturing method, mounting by batch process with surface-mount technology, high light extraction efficiency, and low manufacturing cost are realized. The light-emitting device comprises semiconductor layers of p-type and n-type nitride semiconductor, semiconductor-surface-electrodes to apply currents into each of the semiconductor layers, an insulating layer which holds the semiconductor layers, and mount-surface-electrodes. The semiconductor layers has a non-deposited area where the other semiconductor layer is not deposited. The insulating layer has VIA which electrically connect the mount-surface-electrodes and the semiconductor-surface-electrodes.

Abstract: The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.

Abstract: A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure.

Abstract: A vertical nitride semiconductor light emitting device and a manufacturing method thereof are provided. In the device, an ohmic contact layer, a p-type nitride semiconductor layer, an active layer, an n-type nitride semiconductor layer and an n-electrode are sequentially formed on a conductive substrate. At least one of a surface of the p-type nitride semiconductor layer contacting the ohmic contact layer and a surface of the n-type nitride layer contacting the n-electrode has a high resistance area of damaged nitride single crystal in a substantially central portion thereof. The high resistance area has a Schottky junction with at least one of the ohmic contact layer and the n-electrode.

Abstract: A semiconductor device includes a semiconductor substrate with a pattern region and a dummy region, an interlayer dielectric film arranged on the semiconductor substrate, a semiconductor layer pattern arranged on the interlayer dielectric film in the pattern region, a dummy pattern arranged on the interlayer dielectric film in the dummy region, a contact plug arranged inside the interlayer dielectric film, and the contact plug connecting the semiconductor layer pattern to the semiconductor substrate, and a dummy plug arranged inside the interlayer dielectric film, the dummy plug corresponding to the dummy pattern. A method for fabricating the semiconductor device includes forming these structures.

Abstract: A uniform high brightness light source is provided using a plurality of light emitting diode (LED) chips with slightly different pump wavelengths with a wavelength converting element that includes at least two different wavelength converting materials that convert the light to different colors of light. The intensity of the light produced by the LED chips may be varied to provide a tunable CCT white point. The wavelength converting element may be, e.g., a stack or mixture of phosphor or luminescent ceramics. Moreover, the manufacturing process of the light source is simplified because the LED chips are all manufactured using the same technology eliminating the need to manufacture different types of chips.

Abstract: A semiconductor device is provided with: a semiconductor substrate of a predetermined electroconduction type; a hetero semiconductor region contacted with a first main surface of the semiconductor substrate and comprising a semiconductor material having a bandgap different from that of the semiconductor substrate; a gate electrode formed through a gate insulator layer at a position adjacent to a junction region between the hetero semiconductor region and the semiconductor substrate; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor substrate; wherein the hetero semiconductor region includes a contact portion contacted with the source electrode, at least a partial region of the contact portion is of the same electroconduction type as the electroconduction type of the semiconductor substrate, and the partial region has an impurity concentration higher than an impurity concentration of at least that partial region of a gate-electrode facing port

Abstract: A semiconductor optical receiver device is provided, which a mesa comprising a plurality of semiconductor crystal layers formed on a semiconductor substrate including a pn junction having a first conductive semiconductor crystal layer and a second conductive semiconductor crystal layer and including a first contact layer on the semiconductor substrate, a plurality of electrodes to apply electric field to the pn junction are coupled on the semiconductor substrate, a second contact layer is formed on a buried layer in which the mesa is buried, and the electric field is applied to the pn junction through the first and second contact layers.

Abstract: GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid.

Abstract: A wiring substrate in which a capacitor is provided, the capacitor comprising a capacitor body including a plurality of dielectric layers and internal electrode layers provided between the different dielectric layers, wherein said capacitor body has, in at least one side face of said capacitor body, recesses extending in a thickness direction of said capacitor body from at least one of a first principal face of said capacitor body and a second principal face positioned on the side opposite to the first principal face.

Abstract: Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.

Abstract: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.

Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

Abstract: Gold wire for connecting a semiconductor chip basically containing praseodymium in 0.0004 mass % to 0.02 mass % in range and, considering the bonding characteristics, containing beryllium or aluminum or both in limited ranges and, considering the precipitates formed in the gold wire, further containing auxiliary additive elements of calcium, lanthanum, cerium, neodymium, and samarium in limited ranges.

Abstract: A ceramic substrate for mounting a light emitting element. The ceramic substrate has a placement surface for placing a light emitting element having an electrode; and an electrode electrically-connected with the electrode of the light emitting element, wherein the ceramic substrate comprises a substrate body consisting of a nitride ceramics; and a coat layer coating at least a part of a surface of the substrate body and consisting of a ceramics different from the nitride ceramics forming the substrate body; and the coat layer has an optical reflectance of 50% or more for any light having a wavelength of from 300 to 800 nm, which can increase a luminance of the light emitting element by reflecting the light emitted from the element efficiently with certainty, and which has a high heat radiation property; and a manufacturing method therefor.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a die-side surface including a die-attach region; a system of interconnects extending through the substrate panel and adapted to allow a connection of the substrate to external circuitry; and a plurality of solder bumps including: die-attach solder bumps electrically coupled to the system of interconnects and disposed in the die-attach region; and barrier solder bumps isolated from the system of interconnects, the barrier solder bumps being disposed outside of the die-attach region and being adapted to substantially limit a flow of underfill away from the die-attach region.

Abstract: A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die.

Abstract: An electronic device can include a first radiation region, a second radiation region spaced apart from the first radiation region, and an insulating region. The insulating region can have a first side and a second side opposite the first side. The first radiation region can lie immediately adjacent to the first side, and the second radiation region can lie immediately adjacent to the second side. Within the insulating region, no other radiation region may lie between the first and second radiation regions, and the insulating region can include an insulating layer that includes a plurality of openings. In another aspect, a process for forming the electronic device can include patterning an insulating layer.

Abstract: It is an object of the present invention to provide a technology of controlling a threshold voltage of a thin film transistor in which an amorphous oxide film is applied to a channel layer. There is provided a semiconductor apparatus including a plurality of kinds of transistors, each of the plurality of kinds of transistors including a channel layer made of an amorphous oxide containing a plurality of kinds of metal elements; and threshold voltages of the plurality of kinds of transistors are different from one another by changing an element ratio of the amorphous oxide.