Abstract: There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.

Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

Abstract: A non-volatile memory (NVM) circuit includes at least two types of NVM sub-circuits that share common support circuitry. Different types of NVM sub-circuits include ordinary NVM circuits that provide a logic output upon being addressed, programmable fuses that provide an output upon transitioning to a power-on state, NVM circuits that provide an ON/OFF state output, and the like. Some of the outputs are used to calibrate circuits within a device following power-on. Other outputs are used to store information to be employed by various circuits.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value.

Abstract: A resistance change type memory includes first, second and third drive lines, a resistance change element having one end connected to the third drive line, a first diode having an anode connected to the first drive line and a cathode connected to other end of the first resistance change element, a second diode having an anode connected to other end of the first resistance change element and a cathode connected to the second drive line, and a driver/sinker which supplies a write current to the resistance change element. A write control circuit is arranged such that when first data is written, the write current is caused to flow in a direction from the first drive line to the third drive line, and when second data is written, the write current is caused to flow in a direction from the third drive line to the second drive line.

Abstract: A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

Abstract: Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability.

Abstract: A method for fabricating an integrated circuit, the method comprises forming a first electrode, depositing resistance changing material over the first electrode, the resistance changing material having an active zone for switching the resistance of the resistance changing material and an inactive zone, and forming a second electrode over the resistance changing material. The chemical composition of the resistance changing material in the active zone differs from the chemical composition of the resistance changing material in the inactive zone.

Abstract: An output data strobe signal generating method and a memory system that includes a plurality of semiconductor memory devices, and a memory controller for controlling the semiconductor memory devices, wherein the memory controller provides a command signal and a chip selecting signal to the semiconductor memory devices. One or more of the semiconductor memory devices may detect a read command and a dummy read command in response to the command signal and the chip selecting signal and generate one or more preamble signals based on a calculated preamble cycle number.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: A semiconductor integrated circuit device capable of shortening a chip reset period (time) is provided. The semiconductor integrated circuit device has a nonvolatile memory which performs a reading operation of trimming information after completion of precharge of a data line, and a power-on reset circuit (64) which starts an operation in response to power-on to reset a control circuit of the nonvolatile memory. The device further has a power-on precharge circuit (66) which starts an operation in response to the power-on to perform the precharge operation of the data line. The power-on reset circuit (64) includes a first CR operation circuit (642) which produces a reset release signal indicative of change of a voltage level at a time point when a first predetermined time period (T1) elapses from the power-on.

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract: A method for data storage includes storing data in a group of analog memory cells by writing respective first storage values into the memory cells. After storing the data, respective second storage values are read from the memory cells. A subset of the memory cells, in which the respective second storage values have drifted below a minimum readable value, is identified. The memory cells in the subset are operated on, so as to cause the second storage values of at least one of the memory cells in the subset to exceed the minimum readable value. At least the modified second storage values are re-read so as to reconstruct the stored data.

Abstract: A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.

Abstract: A ferroelectric memory includes a memory cell array including a first unit block, a second unit block, and a plurality of dummy cells. The plurality of dummy cells being arranged toward a column direction and being disposed between the first unit block and the second unit block. The first unit block including a plurality of first memory cells arranging in t rows, and including a plurality of first plate lines arranging toward a row direction. The second unit block including a plurality of second memory cells arranged in t rows, and including a plurality of second plate lines arranging toward a row direction. Each of the plurality of dummy cells including a ferroelectric capacitor. Either of the first second plate line or the second plate line of the second unit block extending above the plurality of dummy cells.

Abstract: A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.

Abstract: Provided is a method of inverting data that is to be transmitted and transmitting the data in a semiconductor device. The method includes inverting bits of data that is to be transmitted if the number of bit transitions of previously transmitted data and the data that is to be transmitted among sequentially transmitted data exceeds a reference number; indicating in any one of a plurality of data strobe signals that the data that is to be transmitted is inverted; and transmitting the data strobe signal indicating that the data that is to be transmitted is inverted and the inverted data.

Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.

Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.