Abstract: Circuits and methods to minimize power required for sensing and precharge of DRAMs have been achieved. A control circuit ensures that during READ operations the duration of sensing of DRAM cell and precharging is kept to a minimum. A test DRAM cell is used to determine the exact time required for data sensing. Furthermore no precharging is performed during WRITE-operations. In case data is changing from “1” to “0” or vice versa data lines are inverted accordingly during WRITE operation.

Abstract: A block decoding circuit of a semiconductor memory device includes a plurality of block decoders, a plurality of repair address check circuits, a dummy repair address check circuit and a block selection signal generation circuit. The plurality of block decoders are configured to decode a received block selection address. The plurality of repair address check circuits are configured to generate second output signals based on whether a received block selection address and word line selection address are repair addresses. The dummy repair address check circuit is configured to generate a control signal in response to the block selection address and the word line selection address. The block selection signal generation circuit is configured to generate block selection signals based on the first output signals from the plurality of block decoders, the control signal from the dummy repair address circuit, and the second output signals from the repair address check circuits.

Abstract: A first timing control unit controls an active timing of a first control signal to output a first driving control signal. A first data input/output unit transmits write data from a data input/output buffer to a global input/output line or transmits read data from the global input/output line to the data input/output buffer, in response to the first driving control signal. A second timing control unit controls an active timing of a second control signal to output a second driving control signal. A second data input/output unit transmits the write data from the global input/output line to a local input/output line or transmits the read data from the local input/output line to the global input/output line, in response to the second driving control signal.

Abstract: A sense amplifier is disclosed. One embodiment is a sensing circuit that includes a sensing device and a sense transistor coupled to the sensing device. A first switch that is coupled to the sense transistor and to the sensing device causes the sensing device to be charged to a first voltage that is a function of the threshold voltage of the sense transistor. One or more second switches that are coupled to the sensing device and to a target element. The second switches couple the sensing device to the target element to modify the first voltage on the sensing device and decouple the target element from the sensing device during a sense phase in which the modified first voltage is applied to the sense transistor. A condition of the target element is determined based on whether or not the sense transistor turns on in response to applying the modified first voltage to the sense transistor.

Abstract: A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop) clock so as to generate an even-numbered divided clock and an odd-numbered divided clock. An even-numbered output enable signal generator generates an even-numbered output enable signal on the basis of an external read command, the timing signal, a CL (CAS Latency), and the even-numbered divided clock. An odd-numbered output enable signal generator generates an odd-numbered output enable signal on the basis of the external read command, a timing signal in which the timing signal is inverted, the CL, and the odd-numbered divided clock. A logical unit logically operates the even-numbered output enable signal and the odd-numbered output enable signal and outputs an output enable signal.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.

Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Abstract: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a bank address counter that holds a bank address for selecting a memory bank to be refreshed, counts up the bank address every time the refresh command signal is output, and performs a carry-over action when count-up operations equivalent to the number of the memory banks are performed; and a row address counter that holds a row address for selecting a word line to be refreshed, and counts up the row address in response to the carry-over action.

Abstract: A semiconductor memory device includes a first inverter ad a second inverter, a first power supply control circuit, and a second power supply control circuit. The first and second inverters constitute a memory cell and each have an input terminal and an output terminal connected crosswise to an output terminal and an input terminal, respectively, of the other. The first power supply control circuit supplies a first voltage to the first inverter. The second power supply control circuit supplies a second voltage to the second inverter. The first and second power supply control circuits control the first and second voltages, respectively, supplied to the first and second inverters in a selected memory cell for a writing operation in accordance with write data.

Abstract: Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage.

Abstract: Disclosed is a regulator including: a differential amplifier having a differential input stage receiving a reference voltage and an output terminal voltage, a push-pull type output portion of a current mirror configuration, a drive transistor having a control terminal connected to an output portion of the differential amplifier, first and second transistors cascode-connected between a control terminal of the drive transistor and a power supply, and third and fourth transistors cascode-connected between the control terminal of the drive transistor and ground. Control terminals of the first and the third transistors are respectively connected to control terminals of the push-pull transistors, control terminals of the second and fourth transistors are respectively connected to a first and a second control signal.

Abstract: The semiconductor memory device includes a reset control circuit that monitors a reset signal at an enablement time point of the reset signal input and outputs monitoring signals corresponding to a state of the reset signal. The reset control unit also enables and outputs a reset control signal when the states of the monitoring signals are equal, and ends the monitoring of the reset signal in synchronization with the enablement of the reset control signal. An internal circuit receives the reset control signal, and the reset control signal controls the initialization of the internal circuit. When the reset signal maintains the enablement state for a predetermined period, the reset control signal is enabled, making it possible to prevent reset malfunction associated with a glitch occurring in the reset signal.

Abstract: A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module receives the latch control signal, a data input signal, and the at least one voltage supply signal. The latch module selectively stores data associated with the data input signal based on the latch control signal. The latch module selectively changes the at least one voltage supply signal from a first level to a second level and outputs the data according to the second level based on the latch control signal.

Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry.

Abstract: A phase change memory includes a float buffer which stores the result of a comparison between the current state of data in the phase change memory cells and an intended next state of each of those cells. The float buffer indicates which cells need to be programmed in order to achieve the new states and which cells happen to already be in the new states. Then, after programming of the cells, the float buffer indicates which cells still need to be programmed. Thus, a control stage uses the information in the float buffer to program only those cells whose states need to be changed.

Abstract: The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of multi-level memory cells connected in series. The plurality of multi-level memory cells forms a plurality of threshold distributions each of which corresponds to a status of a lower bit and a status of an upper bit, wherein a lower bit and an upper bit constitute a lower page and an upper page respectively. The status of the lower bit dichotomizes the threshold distributions into two groups and the status of the upper bit further dichotomizes each of two groups. When programming a memory cell of the upper page, higher potentials are applied to a non-selected word line adjacent to the selected word line than those applied to the non-selected word line when programming the memory cell of the lower page.

Abstract: A method and apparatus are provided for adaptive memory cell overerase compensation. A semiconductor memory device (100) is provided for performing the adaptively compensating erase verify operation (500, 600). The memory device (100) includes at least one word line (402). One or more memory cells (200) and one or more reference cells (406, 408) are connected to the word lines (402), where the one or more reference cells (406, 408) include an erased reference cell (408) connected to each word line (402). The method (500, 600) for adaptive memory cell overerase compensation includes determining an erase verify gate voltage (506, 608) utilizing the erased reference cell(s) (408) and verifying an erase voltage (514) of the memory cells (200) in response to the erase verify gate voltage (512, 614).

Abstract: A memory card and a non-volatile memory controller thereof are provided. The non-volatile memory controller includes a firmware download port group, a memory interface unit, a processing unit, and a host interface unit. The firmware download port group is used for coupled to a firmware update fixture. The memory interface unit includes at least one tri-state buffer component, and the memory interface unit is coupled to a non-volatile memory and the firmware download port group through the tri-state buffer component, wherein the tri-state buffer component determines whether to operate in a high-impedance mode or a normal mode according to a mode single. The processing unit accesses the non-volatile memory through the memory interface unit. When the tri-state buffer component operates in the high-impedance mode according to the mode single, the firmware update fixture writes a new firmware into the non-volatile memory through the firmware download port group.