Patents Examined by Daniel Bernard
  • Patent number: 9342260
    Abstract: Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: May 17, 2016
    Assignee: OCZ Storage Solutions Inc.
    Inventors: Franz Michael Schuette, William Ward Clawson
  • Patent number: 9158693
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Patent number: 9135164
    Abstract: First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 15, 2015
    Assignee: Virident Systems Inc.
    Inventors: Vijay Karamcheti, Shibabrata Mondal, Swamy Gowda
  • Patent number: 9122588
    Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 1, 2015
    Assignee: Virident Systems Inc.
    Inventors: Shibabrata Mondal, Vijay Karamcheti, Ankur Arora, Ajit Yagaty
  • Patent number: 9122592
    Abstract: In one aspect, a method of writing data in a flash memory system is provided. The flash memory system forms an address mapping pattern according to a log block mapping scheme. The method includes determining a writing pattern of data to be written in a log block, and allocating one of SLC and MLC blocks to the log block in accordance with the writing pattern of the data.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: September 1, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Moon Cheon, Seon-Taek Kim, Chan-Ik Park, Sung-up Choi
  • Patent number: 9116623
    Abstract: A method, system and computer program product for optimizing storage system behavior in a cloud computing environment. An Input/Output (I/O) operation data is appended with a tag, where the tag indicates a class of data for the I/O operation data. Upon the storage controller reviewing the tag appended to the I/O operation data, the storage controller performs a table look-up for the storage policy associated with the determined class of data. The storage controller applies a map to determine a storage location for the I/O operation data in a drive device, where the map represents a logical volume which indicates a range of block data that is to be excluded for being stored on the drive device and a range of block data that is to be considered for being stored on the drive device. In this manner, granularity of storage policies is provided in a cloud computing environment.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: August 25, 2015
    Assignee: International Business Machines Corporation
    Inventors: Rohith K. Ashok, Darryl E. Gardner, Ivan M. Heninger, Douglas A. Larson, Gerald F. McBrearty, Aaron J. Quirk, Matthew J. Sheard
  • Patent number: 9104532
    Abstract: Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag value associated with the queue entry and specifying a position from which to extract a first subset of the data values is read. The queue entry is populated with the first subset of the data values starting at the position specified by the tag value. The processing element determines whether a second subset of the data values in the first group of data values is associated with a subsequent queue entry, and populates a portion of the subsequent queue entry with the second subset of the data values.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair
  • Patent number: 9098417
    Abstract: Some embodiments include a partitioning mechanism that partitions a cache memory into sub-partitions for sub-entities. In the described embodiments, the cache memory is initially partitioned into two or more partitions for one or more corresponding entities. During a partitioning operation, the partitioning mechanism is configured to partition one or more of the partitions in the cache memory into two or more sub-partitions for one or more sub-entities of a corresponding entity. A cache controller then uses a corresponding sub-partition for memory accesses by the one or more sub-entities.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: August 4, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Gabriel H. Loh, Jaewoong Sim
  • Patent number: 9092387
    Abstract: A non-volatile memory may operate, not in a master/slave arrangement, but in a peer-to-peer arrangement. In some embodiments, the memory may initiate a transaction with a device outside the memory. Thus, the memory may proactively perform tasks conventionally performed by memory controllers and other external devices.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: July 28, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Nathan Chrisman
  • Patent number: 9081510
    Abstract: Described is a technology by which a virtual hard disk is migrated from a source storage location to a target storage location without needing any shared physical storage, in which a machine may continue to use the virtual hard disk during migration. This facilitates use the virtual hard disk in conjunction with live-migrating a virtual machine. Virtual hard disk migration may occur fully before or after the virtual machine is migrated to the target host, or partially before and partially after virtual machine migration. Background copying, sending of write-through data, and/or servicing read requests may be used in the migration. Also described is throttling data writes and/or data communication to manage the migration of the virtual hard disk.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 14, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dustin L. Green, Jacob K. Oshins, Lars Reuther
  • Patent number: 9081665
    Abstract: A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: July 14, 2015
    Assignee: OCZ Storage Solutions Inc.
    Inventors: Franz Michael Schuette, Yaron Klein, Hyun Mo Chung
  • Patent number: 9069660
    Abstract: Systems and methods for writing to high-capacity memory are disclosed. In high-capacity memory systems in which the capacity of the characteristic portion of the memory (e.g., a page of NAND flash memory) exceeds the capacity of a buffer used to write to the memory, underutilization issues are prevalent. Data organized in the buffer can be combined with additional data to improve utilization of the characteristic portion. According to various embodiments, the additional data can include duplicate copies of the data, whitened data, or any other suitable type of data.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 30, 2015
    Assignee: APPLE INC.
    Inventors: Nir Jacob Wakrat, Matthew J. Byom
  • Patent number: 9069701
    Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache including a cache controller (122); and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit is adapted to create a log (200) in the memory prior to running the virtual machine in said first operating mode; the cache controller is adapted to transfer a modified cache line from the cache to the memory; and write only the memory address of the transferred modified cache line in the log; and the processor unit is further adapted to update a further image of the virtual machine in a different memory location, e.g. on another computer system, by retrieving the memory addresses stored in the log, retrieve the modified cache lines from the memory addresses and update the further image with said modifications.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, William J. Starke
  • Patent number: 9069482
    Abstract: Disclosed are systems and methods for performing backup and recovery operations. An indication may be received, where the indication indicates that a first backup or recovery operation should be performed for at least one storage location. The storage location may be associated with a software application configured to provide backup and recovery services for the at least one storage location. A plurality of resources may be identified, where the plurality of resources is a pool of resources configured to store a backup of one or more data values stored in the at least one storage location. A first resource of the plurality of resources may be selected as a target of the backup or recovery operation. In various implementations, the first resource is selected based on one or more performance capabilities of at least one resource of the plurality of resources.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 30, 2015
    Assignee: EMC CORPORATION
    Inventors: Shelesh Chopra, Joe Putti
  • Patent number: 9063895
    Abstract: Described is non-disruptive data migration from a source array to a heterogeneous destination array. A name server database is queried to obtain port names for each source array port. The source array is queried to obtain information about each source array LUN. A target array is generated at the destination array for receiving a copy of data resident at the source array. The target array has at least as many ports and at least as many LUNs as the source array. Each source array LUN corresponds to a target array LUN and is equal in storage capacity as that corresponding LUN. All data resident in the source array LUNs are copied to corresponding target array LUNs. The name server database is reconfigured to associate source port names with the port addresses of the target array such that the target array appears to a host as the source array.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 23, 2015
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, Adi Ofer, Jeffrey A. Brown
  • Patent number: 9063900
    Abstract: An information processing apparatus connected to a first storage device and a second storage device via a storage control device, the information processing apparatus includes a transfer unit configured to cause the storage control device to transfer to a rebuilding state after the setting unit has set the password for the second storage device.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 23, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takeru Imamura
  • Patent number: 9063896
    Abstract: Described is non-disruptive data migration from a source virtual array at a source storage array to a target virtual array at a heterogeneous destination storage array. A name server database is queried to obtain port names for each source port. The source storage array is queried to obtain information about each source virtual array LUN. A target virtual array is generated at the destination array for receiving a copy of data resident at the source virtual array. The target virtual array has at least as many ports and at least as many LUNs as the source virtual array. Data resident in the source virtual array LUNs are copied to corresponding target virtual array LUNs. The name server database is reconfigured to associate source port names with the virtual port addresses of the target virtual array such that the target virtual array appears to a host as the source virtual array.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 23, 2015
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, Adi Ofer, Jeffrey A. Brown
  • Patent number: 9058195
    Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Ghai, Guy L. Guthrie, Geraint North, William J. Starke, Phillip G. Williams
  • Patent number: 9053065
    Abstract: A process for lazy checkpointing is enhanced to reduce the number of read/write accesses to the checkpoint file and thereby speed up the checkpointing process. The process for restoring a state of a virtual machine (VM) running in a physical machine from a checkpoint file that is maintained in persistent storage includes the steps of detecting access to a memory page of the virtual machine that has not been read into physical memory of the VM from the checkpoint file, determining a storage block of the checkpoint file to which the accessed memory page maps, writing contents of the storage block in a buffer, and copying contents of a block of memory pages that includes the accessed memory page from the buffer to corresponding locations of the memory pages in the physical memory of the VM. The storage block of the checkpoint file may be compressed or uncompressed.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: June 9, 2015
    Assignee: VMware, Inc.
    Inventors: Alexander Thomas Garthwaite, Yury Baskakov, Irene Zhang, Kevin Scott Christopher, Jesse Pool
  • Patent number: 9053064
    Abstract: A process for lazy checkpointing a virtual machine is enhanced to reduce the number of read/write accesses to the checkpoint file and thereby speed up the checkpointing process. The process for saving a state of a virtual machine running in a physical machine to a checkpoint file maintained in persistent storage includes the steps of copying contents of a block of memory pages, which may be compressed, into a staging buffer, determining after the copying if the buffer is full, and upon determining that the buffer is full, saving the buffer contents in a storage block of the checkpoint file.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: June 9, 2015
    Assignee: VMware, Inc.
    Inventors: Alexander Thomas Garthwaite, Yury Baskakov, Irene Zhang, Kevin Scott Christopher, Jesse Pool