Abstract: A method for controlling a switch apparatus connectable to a host and a storage device including first and second areas, the method includes: establishing schedule of copying data stored in the first area of the storage device into the second area of the storage device; monitoring a state of access by the host to the storage device; carrying out copying the data stored in the first area into the second area while the monitored state of the access by the host allows copying of the data from the first area into the second area; and enhancing copying, if any portion of the data remains when a time set by the schedule is expired, the remaining portion of the data from the first area into the second area.

Abstract: Methods and apparatuses are disclosed for improving speculation success in processors. In some embodiments, the method may include executing a plurality of threads of program code, the plurality of threads comprising a first speculative load request, setting an indicator bit corresponding to a cache line in response to the first speculative load request, and in the event that a second speculative load request from the plurality of threads refers to a first cache line with the indicator bit set, determining if a second cache line is available.

Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

Abstract: A method, system and computer program product are provided for implementing feedback directed Non-Uniform Memory Access (NUMA) mitigation tuning in a computer system. During a page frame memory allocation for a process, predefined monitored performance metrics are compared with stored threshold values. Responsive to the compared values, selected use of local memory is dynamically modified during the page frame memory allocation.

Abstract: A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.

Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.

Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to optimize data remanence over hybrid disk clusters using various storage technologies, determine one or more data storage technologies accessible by a file system, and determine secure delete rules for each of the one or more storage technologies accessible by the file system. The secure delete rules include a number of overwrites required for data to be securely deleted from each of the one or more storage technologies. The programming instructions are further operable to provide the secure delete rules to the file system upon a request for deletion of data for each of the one or more storage technologies a specific amount of times germane to secure delete data from the one or more storage technologies.

Abstract: A virtual disk is comprised of segments of unused capacity of physical computer-readable storage media co-located with computing devices that are communicationally coupled to one another through network communications. The computing devices execute one or more of a client process, a storage process and a controller process. The controller processes manage the metadata of the virtual disk, including a virtual disk topology that defines the relationships between certain ones of the physical computer-readable storage media and a particular virtual disk. The client process provide data for storage to certain ones of the computing devices executing the storage processes, as defined by a virtual disk topology, and also read data from storage from those computing devices. The client process additionally expose the virtual disk in the same manner as any other computer-readable medium.

Abstract: A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.

Abstract: A particular method includes loading one or more memory images into a multi-way cache. The memory images are associated with an audio decoder, and the multi-way cache is accessible to a processor. Each of the memory images is sized not to exceed a page size of the multi-way cache.

Abstract: Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal.

Abstract: Described is a technology by which a virtual hard disk is migrated from a source storage location to a target storage location without needing any shared physical storage, in which a machine may continue to use the virtual hard disk during migration. This facilitates use the virtual hard disk in conjunction with live-migrating a virtual machine. Virtual hard disk migration may occur fully before or after the virtual machine is migrated to the target host, or partially before and partially after virtual machine migration. Background copying, sending of write-through data, and/or servicing read requests may be used in the migration. Also described is throttling data writes and/or data communication to manage the migration of the virtual hard disk.

Abstract: A storage apparatus includes: a memory allowing an operation to be carried out in order to additionally write new write data into a storage area already used for storing previous write data so as to store the new data in the storage area along with the previous write data; an input/output section configured to receive write data in a write access; and a control section configured to write the write data into the memory on the basis of the write access, wherein, in internal processing based on the write access, the control section carries out an additional-write operation for a storage area already used for storing the previous write data in the internal processing.

Abstract: Time managed read and write access to a data storage device. As a part of time managed read and write access to a data storage device, a request for read and/or write access to the data storage device is accessed and it is determined whether the request for read and/or write access to the data storage device is to be granted. Based on the determination, read and/or write access to the data storage device is either allowed or blocked. If read and/or write access is allowed, read and/or write access is terminated after passage of a predetermined period of time.

Abstract: As apparatus and associated method for a dual active-active array storage system with a first controller with top level control of a first memory space and a second controller with top level control of a second memory space different than the first memory space. A seek manager residing in only one of the controllers defines individual command profiles derived from a combined list of data transfer requests from both controllers. A policy engine continuously collects qualitative information about a network load to both controllers to dynamically characterize the load, and governs the seek manager to continuously correlate each command profile in relation to the load characterization.

Abstract: A method of operating a data management system includes establishing a base state for a data storage volume, generating a list of blocks associated with the data storage volume that have changed, and creating a snapshot from the list of blocks.

Abstract: Disclosed is a method of collapsing a derivative version of a primary storage volume into the primary storage volume. The method comprises generating the derivative version of the primary storage volume that contains a plurality of data items stored in a secondary storage volume, wherein the derivation version comprises a plurality of blocks, identifying changed blocks of the plurality of blocks that changed as a result of modifying at least one of the data items, identifying which of the changed blocks of the plurality of blocks that changed remain allocated, and collapsing the derivative version of the primary storage volume into the primary storage volume by copying those blocks identified as changed and allocated to the primary storage volume.

Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

Abstract: A programming and debugging system identifies one or more statically-allocated symbols in a symbol table for an inferior process. The statically-allocated symbols pertain to one or more structures for the inferior process. The inferior process has dynamic memory allocations in an inferior process memory space. The symbol table comprises data used to categorize the statically-allocated area of memory. The system locates the structures in the inferior process memory space and determines whether an address of the structures in the inferior process memory space matches an address of a block of the dynamically allocated area of memory. The system categorizes the block of dynamically allocated memory based on the determination of whether an address of the structures matches an address of a block of the dynamically allocated area of memory.

Abstract: A method and system for manipulating a spin state of each disk in a drive array is disclosed. In one embodiment, a method includes monitoring input/output (I/O) requests to each disk drive in a disk array and identifying any disk drive as an inactive disk drive based on a number of I/O requests directed to said any disk drive for a given time interval. The method further includes moving data from the inactive disk drive to an active disk drive having a free disk space to store the data and updating metadata associated with the data using a log-structured file system for the disk array. Further, the method includes manipulating a spin state of the inactive disk drive by spinning down the inactive disk drive to conserve power. Furthermore, the method includes redirecting subsequent I/O requests for the inactive disk drive to the active disk drive by accessing the metadata of the log-structured file system.