Patents Examined by Daniel C Puentes
  • Patent number: 10389346
    Abstract: A circuit may include a switching element configured to draw a positive current from a source/sink unit when the switching element is turned on, the source/sink unit including an inductance, the inductance emitting an excess positive current after the switching element is turned off. Additionally, the circuit may include a snubber circuit configured to absorb the excess positive current from the inductance of the source/sink unit, and deliver a negative current to the source/sink unit. In one example, the delivered negative current has a lower amperage and a longer duration than the positive current.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Uwe Kirchner, Stefano De Filippis
  • Patent number: 10389236
    Abstract: A power converter that supplies a constant output voltage includes a regulator that connects to a charge pump. The charge pump is operable in plural charge-pump modes. A controller preemptively suppress evidence of occurrence of a transition between said charge-pump modes.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 20, 2019
    Assignee: pSemi Corporation
    Inventors: Aichen Low, Gregory Szczeszynski
  • Patent number: 10389343
    Abstract: Methods and apparatuses have been disclosed for a high speed, low power, isolated buffer having architecture and operation that control current flow to minimize coupling and power consumption. Buffer architecture may include one or more of BiCMOS components, an input disabling circuit operated to additionally disable an input circuit when it is also disabled by a selection circuit and a buffer disabling circuit operated to disable the buffer when the input circuit is disabled by the selection circuit. Any one or more of these features may be implemented to improve isolation performance. The selection circuit, input disabling circuit and buffer disabling circuit may be operated by the same control signal.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 20, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Chengming He
  • Patent number: 10382023
    Abstract: A clock generating circuit is operated in a phase-locking mode to generate an output clock signal having a first frequency that is phased-locked with respect to a variable-frequency input clock signal. After a frequency transition in the input clock signal, phase-locking is disabled within the clock generating circuit to transition the output clock signal from the first frequency to a second frequency that lacks phase-alignment with the input clock signal, then a frequency-lock range of the clock generating circuit is adjusted to transition the output clock signal from the second frequency to a third frequency that also lacks phase alignment with the input clock signal. After adjusting the frequency-lock range of the clock generating circuit, phase-locking is re-enabled therein to transition the output clock signal from the third frequency to a fourth frequency that is phase-aligned with the variable-frequency input clock signal.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: August 13, 2019
    Assignee: Rambus Inc.
    Inventors: Yue Lu, Jared L. Zerbe
  • Patent number: 10382017
    Abstract: Inventive aspects include a dynamic flip flop, comprising a data independent P-stack feedback circuit. The data independent P-stack feedback circuit may include a first P-type transistor gated by a first dynamic inverted net signal, and a second P-type transistor gated by an inverted clock signal. A drain of the second P-type transistor may be coupled to a source of the first P-type transistor. A source of the second P-type transistor may be coupled to a node that is configured to receive a second dynamic inverted net signal. The source of the second P-type transistor may be directly coupled to the node that is configured to receive the second dynamic inverted net signal instead of a constant power source. The data independent P-stack feedback circuit may include one or more delay stages to eliminate race conditions.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: August 13, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Matthew Berzins, Sumanth Suraneni
  • Patent number: 10382025
    Abstract: A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 13, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Robert Callaghan Taft
  • Patent number: 10372180
    Abstract: A factory reset apparatus includes a reset switch, a first power supply module, a flip-flop, and a CPU. The flip-flop includes a data input pin, a clock pin, and a true flip-flop output pin. The reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to the CPU. The reset switch generates a low-level reset signal when being pressed; the flip-flop receives an electrical signal from the clock pin. A rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the reset signal. The flip-flop outputs a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal. The CPU starts a factory reset operation according to the reset request signal.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: August 6, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Ruhong Zhang, Jinbo Ding, Zhengsheng Xie
  • Patent number: 10374587
    Abstract: The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Feldtkeller
  • Patent number: 10374598
    Abstract: A power on reset circuit according to the present disclosure includes: a reference voltage generating circuit that generates a reference voltage, and also outputs, as a control voltage, a voltage at a node at which a voltage rise is slower than the reference voltage; a comparison voltage generating circuit that operates in response to the control voltage output from the reference voltage generating circuit, and outputs a comparison voltage depending on a power source voltage; and a comparison circuit that compares the comparison voltage output from the comparison voltage generating circuit to the reference voltage output from the reference voltage generating circuit, and outputs an operation signal while the comparison voltage exceeds the reference voltage.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: August 6, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kentaro Yasunaka
  • Patent number: 10367505
    Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: July 30, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Prashant Singh
  • Patent number: 10361026
    Abstract: A wireless power transmitting apparatus including a first transmitting coil; a second transmitting coil; a third transmitting coil on the first transmitting coil and the second transmitting coil; and a substrate to accommodate the first transmitting coil, the second transmitting coil, and the third transmitting coil, further the substrate includes a wall to surround a part of an outer circumference of the first transmitting coil and a part of an outer circumference of the second transmitting coil; a first protrusion to surround a first part of an outer circumference of the third transmitting coil; and a second protrusion to surround a second part of the outer circumference of the third transmitting coil.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: July 23, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jay Park, Soon Young Hyun
  • Patent number: 10355693
    Abstract: An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Varun Jain, Brent Duckering
  • Patent number: 10348090
    Abstract: The present invention relates to apparatus 30 for determining a condition of a network section 34 comprised in an electrical power network 32. The network section 34 is configured such that electrical power flows to or from each of plural locations in the network section. The apparatus 30 is configured to receive a first quantity in respect of a first location in the network section 34 and to receive a second quantity in respect of a second location in the network section, each of the first and second quantities corresponding to a signal amplitude and a signal phase angle at its respective location. The apparatus 30 comprises a processor 42 which is operative to determine a condition quantity corresponding to a loading condition of the network section 34 between the first and second locations in dependence on the first and second quantities.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: July 9, 2019
    Assignee: PSYMETRIX LIMITED
    Inventors: David Tse-Chi Wang, Douglas Wilson
  • Patent number: 10340690
    Abstract: An interference suppression stage for a power supply. The interference suppression stage has an input connected to an input module of the power supply, the input module connected to an electrical supply system, an output connected to an output module of the power supply, the output module connected to an electrical load, at least two power paths connected in parallel between input and output, wherein each of the power paths are configured to be switched between an active state and an inactive state, and a control unit configured to switch at least one of the power paths to the inactive state in a saving mode. The control unit switches different power paths alternately in time to inactive in saving mode.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 2, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Fabian Hoffmeister, Josef Plager
  • Patent number: 10339998
    Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: July 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
  • Patent number: 10340896
    Abstract: A signal-switching circuit for use in an electronic system is provided. The electronic system includes a plurality of hardware circuits. The signal-switching circuit includes a control circuit and a switch circuit. The control circuit is arranged to receive a trigger signal generated by a trigger circuit of the electronic system, and change a mode signal generated by the control circuit according to the trigger signal. The switch circuit is arranged to electrically connect transmission signals from one of the hardware circuits to a transmission interface of the electronic system according to the mode signal.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 2, 2019
    Assignee: WIWYNN CORPORATION
    Inventors: Che-Wei Chung, Chia-Nung Tseng, Yung Jung Du
  • Patent number: 10333500
    Abstract: A circuit includes a latch configured to update a stored state of the latch in response to an input data signal and a pulsed clock signal. The circuit includes a pulse generator configured to generate the pulsed clock signal based on an input clock signal, the input data signal, and a feedback signal indicative of a stored state of the latch. The pulse generator may be configured to generate a pulse enable signal based on the input data signal, the input clock signal, and the feedback signal. The pulsed clock signal may be based on the pulse enable signal and the input clock signal. The pulse generator may generate the pulsed clock signal to have a pulse of a first signal level in response to an indication that the stored state of the latch needs to change and generates the pulsed clock signal to have a second signal level, otherwise.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: June 25, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David Scott Vickers, Patrick J. Shyvers
  • Patent number: 10333497
    Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anil Kumar, Mahbub Rashed, Sushama Davar, Navneet Jain
  • Patent number: 10333532
    Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yasuo Satoh
  • Patent number: 10333511
    Abstract: An integrated circuit (IC) including a first power-on reset (POR) circuit and a second POR circuit is disclosed. The first POR circuit is configured to enable the second POR circuit when a supply voltage initially exceeds a first threshold voltage as the supply voltage is being applied to the IC. The second POR circuit is configured to activate a first section of circuitry when the second POR circuit is enabled by the first POR circuit and the supply voltage initially exceeds a second threshold voltage as the supply voltage is being applied to the IC. Since a POR threshold voltage can affect current drain and/or operational functions of an IC, having the first POR circuit configured to enable the second POR circuit and having the second POR circuit configured to activate the first section of the main circuitry allows the IC to operate properly while reducing current drain.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Alexander Wayne Hietala, Christopher Truong Ngo, Praveen Varma Nadimpalli