Abstract: A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

Abstract: An apparatus is provided comprising a first t-switch, which includes an input port arranged to be connected to a first voltage source, a center-tap port, and an output port arranged to be connected to a load. The first t-switch is configured to connect the input port to the output port in an on mode and disconnect the input port from the output port in an off mode. The apparatus further comprises a bias voltage generation circuit configured to generate a bias voltage, the generated bias voltage coupled to the center-tap port of the first t-switch, the bias voltage determined based upon an output port voltage.

Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.

Abstract: Systems, devices, and methods related to phase shifters are provided. An example apparatus includes a first node to receive an input signal, a second node, a first signal path coupled between the first node and the second node, and a second signal path coupled between the first node and the second node. The first signal path includes a positively coupled transformer. The second signal path includes a negatively coupled transformer. The second signal path is out-of-phase with the first signal path at the second node. The apparatus further includes a plurality of switches to select the first signal path or the second signal path. The apparatus may further include tuning capacitors to improve phase-shifting performance of the apparatus.

Abstract: The present disclosure relates to a dual-clock generation circuit and method and an electronic device, and relates to the technical field of integrated circuits. The dual-clock generation circuit includes: a first inverter module, configured to access a first signal and output a first clock output signal; a second inverter module, configured to access a second signal and output a second clock output signal, where the first signal and the second signal are opposite clock signals; a first feedforward buffer, disposed between an input terminal of the first inverter module and an output terminal of the second inverter module, and configured to transmit the first signal to compensate for the second clock output signal.

Abstract: A method and device for adjusting the switching speed of a MOSFET are disclosed. The MOSFET is connected to drive switch, the collector of the drive switch is connected to the grid of the MOSFET through the grid resistor, the emitter of the drive switch is grounded through the emitter resistor, and the collector of the drive switch is also connected to the source resistor through the collector resistor, the other end of the source resistor is connected to the source of the MOSFET; the drain of the MOSFET is connected to the current source. The method comprises: obtaining the adjustment target of the switching speed for the MOSFET, determining the first resistance value of the emitter resistor and/or the second resistance value of the collector resistor based on said adjustment target, controlling the operation of the MOSFET according to the adjusted resistance value.

Abstract: Methods, systems, and devices for controlling a variable capacitor. One aspect features a variable capacitance device that includes a capacitor, a first transistor, a second transistor, and control circuitry. The control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations including detecting a zero-crossing of an input current at a first time. Switching off the first transistor. Estimating a first delay period for switching the first transistor on when a voltage across the capacitor is zero. Switching on the first transistor after the first delay period from the first time. Detecting a zero-crossing of the input current at a second time. Switching off the second transistor. Estimating a second delay period for switching the second transistor on when a voltage across the capacitor is zero. Switching on the second transistor after the second delay period from the second time.

Abstract: An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

Abstract: A method and apparatus for implementing a neural network model in a heterogeneous computing platform are disclosed. The method includes partitioning a neural network model into first sub-models based on a partition standard, obtaining second sub-models by merging at least a portion of the first sub-models based on characteristics of the first sub-models, and deploying the second sub-models.

Abstract: One embodiment provides for a method of transmitting data between multiple compute nodes of a distributed compute system, the method comprising creating a global view of communication operations to be performed between the multiple compute nodes of the distributed compute system, the global view created using information specific to a machine learning model associated with the distributed compute system; using the global view to determine a communication cost of the communication operations; and automatically determining a number of network endpoints for use in transmitting the data between the multiple compute nodes of the distributed compute system.

Abstract: The present disclosure concerns a method and a circuit for controlling first and second switches electrically in series, wherein one or a plurality of crossings of a voltage threshold by a voltage across the first switch cause a conductive state of the second switch.

Abstract: The present disclosure includes apparatuses and methods for operating neural networks. An example apparatus includes a plurality of neural networks, wherein the plurality of neural networks are configured to receive a particular portion of data and wherein each of the plurality of neural networks are configured to operate on the particular portion of data during a particular time period to make a determination regarding a characteristic of the particular portion of data.

Abstract: A bootstrap circuit supporting fast charging and discharging and a chip. A voltage measurement module (12) and a switch module (11) are arranged, and the voltage measurement module (12) controls an operating state of the switch module (11); during charging, under a specific condition, the switch module (11) is enabled to be in an on state so as to achieve fast charging of a voltage output end; and during discharging, the purpose of fast discharging is achieved by means of a second field effect transistor (MP5) arranged in the bootstrap circuit.

Abstract: An apparatus comprises a power source connected to a buffer capacitor. The apparatus comprises a first switch connected between the buffer capacitor and a driven switch. The buffer capacitor is charged by the power source when the first switch is turned off. The apparatus comprises a comparator. The comparator monitors the charging of the buffer capacitor. In response to the buffer capacitor reaching a threshold amount of charge, the comparator turns on the first switch to initiate a charge redistribution of charge from the buffer capacitor to the driven switch.

Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

Abstract: A comparator receives a target voltage and a reference voltage at its inverting and non-inverting input terminals, and outputs a signal corresponding to the level relationship between those voltages A node provided on the output side of the comparator is fed with a signal equivalent to the output signal of the comparator. Between the node and the non-inverting input terminal of the comparator, a capacitor is inserted.

Abstract: Aspects of the present relate to reflection type phase shifters for radio frequency (RF) wireless devices. Reflection type phase structures in accordance with aspects described herein can improve device performance with compact configurations, such as where magnetic and capacitive coupling is integrated into a device design to integrate interactions between elements for improved phase shifting performance in a compact design with wideband performance.

Abstract: A method for operating a wireless power transmission system includes providing a driving signal for driving a transmission antenna, the driving signal based, at least, on an operating frequency for the wireless power transmission system. The method includes receiving, by at least one transistor of an amplifier of the wireless power transmission system, the driving signal at a gate of the at least one transistor and inverting a direct current (DC) input power signal to generate an AC wireless signal at the operating frequency. The method includes receiving, at a damping transistor of a damping circuit, damping signals for switching the damping transistor to control signal damping during transmission or receipt of wireless data signals in-band of the AC wireless signal. The method includes selectively damping, by the damping circuit, the AC wireless signals, during transmission of the wireless data signals, based, at least in part, on the damping signals.

Abstract: This disclosure describes systems, methods, and apparatus for generating a multi-level pulsed waveform using a DC section and a power amplifier. To improve DC section efficiency, a master state is used to determine when the rail voltage can be lowered, and to only allow a state assigned as the master state to lower the rail voltage. Selection of the master state is based on (1) any state having to raise the rail voltage to meet a power demand or (2) a state having the highest drive voltage as determined at the end of each pulse cycle. Further, to avoid challenges from integrator controller, drive voltage is carried over from a last state of one pulse cycle to a first state of a next pulse cycle and assignment of master state in the first state of each pulse cycle is not important and can be arbitrarily selected.

Abstract: Optimized memory usage and management is crucial to the overall performance of a neural network (NN) or deep neural network (DNN) computing environment. Using various characteristics of the input data dimension, an apportionment sequence is calculated for the input data to be processed by the NN or DNN that optimizes the efficient use of the local and external memory components. The apportionment sequence can describe how to parcel the input data (and its associated processing parameters—e.g., processing weights) into one or more portions as well as how such portions of input data (and its associated processing parameters) are passed between the local memory, external memory, and processing unit components of the NN or DNN. Additionally, the apportionment sequence can include instructions to store generated output data in the local and/or external memory components so as to optimize the efficient use of the local and/or external memory components.