Abstract: A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decoding them and executing them so that the scalar processing and the vector processing are carried out in overlap.

Abstract: A disk file management system for use in a data processing system that includes at least one disk drive. The disk space is organized on the basis of logical cylinders, with each logical cylinder including a plurality of disk pages and a cylinder control block ("CCB"). Each entry in the CCB corresponds to a page in the CCB's cylinder. Depending on whether a page is allocated to a file or not, the corresponding CCB entry is a file map entry for a file to which the page is allocated or an entry in a free space map. For a given file, each file map entry includes up to two pointers so that the totality of page map entries for the file defines an unbalanced binary tree structure that consists of a sequence of balanced binary trees of increasing size. The free space map for a given cylinder is preferably a chained free space list.

Abstract: A signal generator for generating signals to control a plurality of devices includes a digital computer and a control interface apparatus. The plurality of devices to be controlled is connected in use to the control interface apparatus. The computer has peripheral device select lines, output control lines, and a data output bus. The control interface apparatus is connected to one of the peripheral device select lines, and while it is enabled by that select line it decodes a device address on the data output bus under the control of one of the output control lines so as to select one of the plurality of devices connected to the interface apparatus, the number of the plurality of devices connected to the interface apparatus thus being limited only by the capacity of the data output bus.

Abstract: A method and apparatus for addressing a peripheral interface by mapping into the memory address space of a processor contained in a peripheral controller. The processor in the peripheral controller initializes interface logic within the peripheral controller and in the host system peripheral interface logic to which the peripheral controller is attached to either transmit or receive a block of data. Once initialized, units of data are transmitted across the interface between the peripheral controller and host system using a strobe and acknowledge signal to indicate when data can be taken or placed on data lines. The processor is placed in a wait state as each unit of data is transferred and a watch dog timer is provided to detect any transfer that is not completed within the normal response time of the interface.

Abstract: A binary number substitution mechanism includes first and second storage arrays addressed by first and second portions, respectively, of an input binary number, producing a substitute output binary number. The input binary number represents a predetermined number of microinstruction addresses in a read-only store, and the output binary number is representative of microinstruction addresses in a main storage device. Only a limited number of the possible input binary numbers are required to access the first and second storage arrays to read out selectively stored binary numbers to create a limited range of output binary numbers unique to each of the limited number of the input binary numbers.

Abstract: An electronic digital dual processor system including an interface to an external memory in addition to an internal memory. The dual processor architecture includes dual independent and simultaneously operable registers for the temporary storage of data from an arithmetic and logic unit and for memory addressing. The internal memory includes a ROM for storing instructions and a RAM for storing data. The internal memory is also used to store instructions. Control and timing circuitry is included for the generation of microinstructions for the instructions stored in the memory. The control and timing circuitry provide for the simultaneous and independent execution of the microinstructions involving the dual register sets.

Abstract: To provide for starting of signal processing operations in a microprocessor (7), for example an automotive-type microprocessor, subject to frequent power interruptions, in which the processing operations are controlled by clock signals from a clock generator (1), and to insure that the microprocessor carries out its computation cycles only after the clock signal generator (1) provides clock signals at an adequate level appropriate for microprocessor operations, the level of the clock signals is sensed, for example in a peak rectifier (2, 3, 5) to reset the microprocessor when the clock signals have reached this level, thereby insuring commencing of processing cycles from a predetermined condition or state of the microprocessor at a time when adequate clock signals are available.

Abstract: A portable electronic testing apparatus for examining the data at a selected address within a microprocessor system and with the microprocessor system including a receptacle for receiving a CPU having particular electrical connections. An electrical socket, having the particular electrical connections for receiving the CPU, provides electrical contact to the CPU when the CPU is removed from the microprocessor system and plugged into the electrical socket. A connector assembly is interconnected with the electrical socket with the connector assembly including a plug simulating the electrical connections of the CPU. The plug is plugged into the receptacle included in the microprocessor system after the CPU is removed from the microprocessor system so as to electrically reconnect the CPU within the operation of the microprocessor system. Address selection switches provide a selection of the address of data to be examined.

Abstract: An input device for a data processor is provided with an input circuit having input keys to designate two or more kinds of functions, an operation unit to perform operational processing in accordance with function inputs from the input circuit, an auxiliary memory to store therein a state of the operation unit, and a memory for a function table wherein the function to be carried out by the operation unit and the state of the operation unit, to which it is to be shifted after completion of the functions, have been previously written in an address to be determined by combination of the input key and the stored contents of the auxiliary memory. One of the two or more kinds of functions assigned to an input key is selectively introduced into the operation unit by the abovementioned input key.

Abstract: A digital processing device fabricated on a single semiconductor substrate includes an electrically programmable memory, a random access memory, a central processing unit, all connected by an information transfer bus. An external interface is provided connected to the information transfer bus to provide information contained on the bus to external devices. At least one security bit is provided to determine the status of data stored in the nonvolatile memory and portions of the random access memory. An external interface inhibit circuit is connected to the external interface. Address logic is connected to the information transfer bus to determine when information contained in the electrically programmable memory or the random access memory is being accessed. The address logic also determines the security status of information stored in the selected portions of the random access memory and the electrically programmable memory.

Abstract: A method is disclosed for assisting the operator of an interactive text processing system to add a list of numbers that have been entered into the system during the creation of a document. The method involves the operator positioning the cursor adjacent the first number in the sequence by operating the cursor move keys. The next step involves the operator pressing and holding either the "column add" or the "row add" function key while watching the movement of the cursor from the first number in the sequence to succeeding numbers in the sequence until the cursor is positioned adjacent the last number in the sequence, at which time the function key is released. The last step in the process is for the operator to press the Enter key which enters the total into the system for subsequent processing and displays the total in the appropriate location on the display.

Abstract: A first location and a last location of the required part of a first piece of picture information displayed at a display part are specified by cursors. Cleared data is transferred to a picture element memory where said picture information is stored for removing unnecessary picture information. The extracted necessary picture information is recorded in a magnetic tape device. Only the necessary part of a second piece of picture information is extracted in a similar manner and is recorded in the magnetic tape device. A logic sum of a title input from the keyboard and said first piece of picture information is obtained for each scanning line to provide a first synthesized picture. A logic sum of the first synthesized picture and said second piece of picture information is obtained for each line to provide a second synthesized picture.

Abstract: Disclosed is a relational algebra engine which has a sort engine, a merge engine, a control processor and a common bus. The sort engine has a plurality of first processing elements which are connected in series. Each first processing element includes first and second buffer memories, a first memory which has a FIFO function, and a first processor which sorts input data elements in accordance with a predetermined rule by using the first and second buffer memories and the first memory which has the FIFO function. The first and second buffer memories and the first memory which has the FIFO function are disposed in parallel. The merge engine has two second processing elements which are disposed in parallel.

Abstract: A digital computer system including a memory and a processor. The memory operates in response to memory commands received from the processor. Items of data stored in the memory include instructions to which the processor responds. Each instruction contains an operation code which belongs to one of several sets of operation codes. The meaning of a given operation code is determined by the operation code set to which the instruction belongs. Some of the instructions also contain names representing items of data used in the operation specified by the operation code. The processor includes an operation code decoding system which decodes the operation code as required for the instruction set to which it belongs, a name resolution system for deriving the address of the data item represented by a name from the name using an architectural base address contained in the name resolution system, and a control system which controls the operation of the processor.

Abstract: A document handling terminal is disclosed having a read unit, a printer, an inscriber and an endorser unit, a printer, an inscriber and an endorser unit. A microprocessor in the terminal controls the operation of the various input output units by means of an operation control table loaded into said microprocessor from a host computer. A plurality of instructions in the table are executed in a sequence without branches or jumps by comparing a condition field in each instruction to information stored in a condition register. If the comparison indicates equal, the operation code of the instruction is executed, otherwise not. The execution of an instruction controls data transfer within a buffer store, between the buffer store and input output registers, the setting of operation indicators and changing of data in the condition register. The input output units are selectively operated according to the state of the operation indicators asynchronous to execution of the instructions.

Abstract: A lock array is provided with bit positions corresponding to each line entry in an associated cache directory. When a lock bit is on, it inhibits the castout, replacement, or invalidation of the associated cache line, which operations are allowed when the lock bit is off. The lock bit may be in an off state while an associated valid bit is set on, but once the lock bit is set on the valid bit cannot be set off until the lock bit is first set off. Lock array controls operate with a replacement selection circuit (which may be conventional) to eliminate each locked line from being a replacement candidate in its congruence class in a set-associative store-in-cache in a multiprocessor (MP). The lock array enables simultaneous reset of all lock bits at each checkpoint without disturbing the status of the associated cache directory. A special type of IE operand request, called a store-interrogate (SI) request, is used to lock the accessed line, whether or not the SI request hits or misses in the cache.

Abstract: A control circuit to disable the operation of a semiconductor microprocessor memory device in the event of an unauthorized attempt to access the memory. A logic circuit generates a control signal in response to receiving a predetermined binary bit pattern of a plurality of chip select signals. The control signal enables the memory device for operation. If the binary bit pattern is not presented, the memory device is disabled for operation.

Abstract: The range of output binary numbers from a number substitution mechanism receiving input binary numbers, and which include first and second storage arrays addressed by first and second of the input binary number is substantially reduced by interleaving alternate output signals from the storage arrays which have been provided selectable binary numbers in certain storage locations accessed by certain ones of the input binary numbers. Further, compression of the range of output of binary numbers as substitution for certain ones of the binary input binary number is achieved by addressing the first and second storage arrays by first and second portions of the input binary number to which a certain number of the input signal line of the first and second portions are common.

Abstract: An automobile radio receiver system includes a control unit located in the passenger compartment and a remote unit, for example, in the trunk compartment of the automobile. The control unit includes a master microcomputer which controls a display and responds to keyboard inputs. The remote unit includes the radio receiver which is controlled by a slave microcomputer. The master and slave microcomputers are interconnected by a single wire data bus. Data regarding keyboard inputs are transmitted to the slave and data regarding receiver status is transmitted to the master. The data is interleaved on a bit by bit basis with master controlling the timing of data transmission thereby permitting a relatively imprecise timing base in the slave.

Abstract: An apparatus for designing three-dimensional structures comprises a unit for recording linear coordinates having a movable support and guideways, crosspiece, carriage and vertical rod which are coupled to one another and which cause displacement along linear coordinates. Sensors of displacement along linear coordinates X, Y, Z are coupled to the guideways, crosspiece, carriage and vertical rod for causing displacement. The apparatus also has an angle joint having three series-connected angle arms for rotation with respect to X, Y, Z axes, respectively. Sensors for recording a change in an angular coordinate .phi., .phi..sub.1, .phi..sub.2, respectively, of rotation with respect to X, Y, Z axes, respectively, are coupled to the angle arms, the point of intersection of X, Y, Z axes of entered coordinates of the movable support coinciding with a point of intersection of X, Y, Z axes of the angle arms for rotation with respect to X, Y, Z axes, respectively.