Abstract: A plurality of first selectors are connected to a branch condition taken/non-taken decision circuit, and a second selector is connected to the first selector. Among branch condition taken/non-taken signals, at least one signal is common to the first selectors. Consequently, the step number of microinstruction to realize a macroinstructions is decreased, and the executing time of the macroinstruction is shortened.

Abstract: The topography of a CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. Five peripheral I/O port buffer circuits are located around the edge of the periphery of the chip, except for an eight bit peripheral output port located along the lower right edge and multiplexed with chip select outputs. The microcomputer includes an eight bit W65CO2S CMOS microprocessor, 192 bytes of SRAM, 4096 bytes of SROM, 22 edge interrupt inputs, 3 level-sensitive interrupt inputs, a UART, serial interface buffer for effectuating correction to a local area token passing network, four timers, and priority interrupt control circuitry. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a "core" of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system.

Abstract: An A output and a B output of a register file 16 are each provided to an associated multiplexer (18,20). Each multiplexer has as a further input a bus (CB00:31) that conveys a result from an ALU 22 via an ALU shifter 28. Outputs of the multiplexers are provided to corresponding A or B inputs of the ALU. Each multiplexer is controlled by an associated register file address comparator (24,26). The address comparators each have as an input corresponding register file A and B update and access addresses. The address comparators compare their associated register file update and access addresses to determine if the register file register selected for access is equal to the register file register selected for update. If these two addresses are found to be equal it is indicated that the result of an ALU operation during an instruction cycle N is to be used as an operand for an ALU operation during a cycle N+1.

Abstract: Apparatus for detecting electrostatic discharge events that may affect operation of a calculator and for suspending the operation of an internal calculator chip before the discharge can corrupt the chip's operation. The apparatus includes an edge detector that detects the discharge event and generates a signal to timer circuitry. The timer circuitry in response generates a signal for a predetermined time to WAIT circuitry which suspends operation of the calculator chip before its calculations can be corrupted. The predetermined time is long enough for the electrostatic discharge to dissipate sufficiently so that it can no longer corrupt the calculations. After the predetermined time passes, the calculator chip resumes its operation to complete its calculations.

Abstract: In a computer system including a central processing unit, a program memory, a control program, a keyboard hardware interrupt handler routine and a single step interrupt handler routine, a method for replacing conventional data from a keyboard with user defined data including placing the central processing unit into single step mode, determining with the single step interrupt handler routine whether a keyboard hardware interrupt handler routine involves a keyboard data input instruction, and, if so, replacing the conventional data with user defined data, followed by either repeating the process or returning the system from single step mode to the main control program.

Abstract: A method for maintaining a selective document history log within a data processing system having multiple resource objects which are accessible by a plurality of users within the data processing system. A history log is created and associated with each resource object for which documentation of selected activities is desired. Next, a list of one or more types of activity is generated and utilized to filter all activities which take place with respect to a particular resource object. Thereafter, documentation of each activity which corresponds to an entry on the list of activities of interest is recorded within the selective document history log. In this manner it is possible to accurately record only those activities of interest such that memory space is more efficiently utilized within the document history log. The system administrator or other manager may limit the authority of a user to establish a document history log.

Abstract: An inertial Navigation System (INS) data interface box allows the transfer of INS data to standard commercial computer (i.e. Personal Computer or PCs) for flexible in-flight use of data received from the INS. The data box includes a means connected to the data bus for changing the INS output from 12 to 5 volts. The data of interest is then applied to a Label/Decode circuit which in turn directs the data to a Write Address Generator circuit which then applies the data to a Page One Memory Buffer circuit. After the data is filed in the Page One Memory Buffer, the Write Address Generator directs a Page Control circuit to turn to a Page Two Memory Buffer to accept the next cycle of data. During the interim data can be read out of the Page One buffer and converted to 8 bit words for applications to the PC. Should the 8 Bits Converter be processing data, "page flips" is inhibited to prevent readout from the Page Two Buffer from mutilating Page One Buffer data as it is being read out.

Abstract: In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

Abstract: Computer system resources shared by several central processing units are allocated by allowing one processing unit to temporarily gain exclusive access to a particular shared resource. Access to a particular resource is controlled by a memory location which contains information representing the current state of the resource and the identity of any processing element currently utilizing the resource. In the case where several resources are interchangeable, the memory location may also contain information regarding the busy/idle states of other interchangeable resources. The memory location can be interrogated by any of the processing elements via command and address information. If the contents of the memory location indicate that the associated resource is not in use, then the interrogating processing element immediately obtains control of the resource.

Abstract: An application program automatically creates and presents a customized user interface. This is done by determining a set of operations which is appropriate for the current user based on various relevant characteristics of the user. The application program presents only the specified operations in the menus, icons, application bars or other interface components of the application program.

Abstract: In a computer system having a configuration which is subject to change, because of failure replacement, updating, or expansion, it is necessary to provide means for loading parameters carrying the present system configuration into the active modules of the system. In this manner, all parallel processors are identified and recognized and depending upon system demands, used because of the parameter loading arrangement of this computer system. Serial lines are provided for loading the parameters into the active modules.

Abstract: A data processing system buffers sequential data for the duration of cyclically recurrent delay times. Memory location allocation is performed in such a way, that the memory is used efficiently without data-shifting after a read-out, and that the address generator is fairly simple.

Abstract: A data transfer bus in a profile and/or dimension measuring system is used to exchange data between plural controllers and plural passive devices and provided with data lines capable of transferring a measurement data signal, a command signal, a status signal, and an address signal corresponding to each unit and a measurement data latch line capable of transferring a measurement data latch line. Thus, an expansion of the system can extremely be facilitated, a detection error of the edge of an object to be measured can be minimized, and high data transfer efficiency can be assured without complication of hardware.

Abstract: A control system for multiple channel data transfers between a main bus and a data bus is provided. A novel input/output processor control which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access conflicts and includes staging buffers coupled to the main bus and data buffers coupled to the data bus. A J-Bus is coupled between the staging buffers and the data buffers and is controlled by J-Bus transfer controller. A D-Bus transfer controller controls information transferred to an from the data bus and the data buffers. An M-Bus transfer controller controls information transferred to and from the staging buffers and the M-Bus. A controllable time slot generator in addition to generating the time slots for transferring information between the data buffers on the J-Bus also provides means for resolving conflicts between the J-Bus and the D-Bus and the M-Bus.

Abstract: A method of extending a hierarchial programming language that retains compatibility with programs written for the original language. This method also allows a language to be defined that permits common commands to be abbreviated into shorter forms, providing a more user friendly system, while still permitting the longer form of a command to perform the intended way. The method also allows such a language to be restructured and extended by inserting a new level into the parse tree of the language. The method comprises inserting a default node into the parse tree of the language at the point where the extension, or the shortened command form, occurs. When the disclosed language parser method interprets the tree, the default node will be treated as if the mnemonic of the default node were actually in the command being parsed at the position where the default node appears in the tree. The disclosed method of processing the new parse tree also allows multiple commands per line, as required by existing standards.

Abstract: The interconnection device attaches to the VMEbus backplane and implements a fully functional AT-compatible computer which is capable of acting as either a master or a slave on the VMEbus. The interconnection device defines a 64K window within the real mode address space of the AT computer which is mapped onto the VMEbus to allow the AT computer to access the VMEbus when in real mode. When the AT computer is in protected mode, addresses above the real mode/protected mode boundary are mapped onto the VMEbus address space. The interface apparatus modifies the AT architecture direct memory addressing (DMA) scheme to allow the microprocessor of the AT computer to act as a VMEbus slave when predefined addresses on the VMEbus are accessed.

Abstract: An apparatus and method is described for converting row-oriented data into column-oriented data. A matrix of row-oriented data is read from a ROM device and stored in a plurality of latches. All the bits from one column of said data is selected from the latches and stored in a register.

Abstract: An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction.

Abstract: A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

Abstract: To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units which are independently controlled and operated in parallel. The classes of instructions include integer instructions, floating point instructions, multiply instructions, and divide instructions. The integer unit, which also performs shift operations, is controlled by the microcode execution unit to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit that services a result queue. When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue.