Abstract: Data processing apparatus performs automatic hardware device identification and system setup in computer systems that have a Programmable Option Select (POS) feature, where the system includes multi-card adapters (adapters with attached daughter card(s)), and/or multi-card planar complexes (system boards with pluggable processor complexes and/or I/O risers). In particular, the apparatus uniquely identifies the aforementioned multi-card devices utilizing unique "combination type" POS IDs, where a combination type POS ID is a POS ID specifically preassigned to a combination of cards rather than to a single type of card. According to the invention, the unique combination type POS ID is partitioned across the combination of cards (for example, hardwired into each card). When the cards are combined, the partitioned ID is synthesized and becomes available to the system.

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.

Abstract: The same data is processed in parallel by a plurality of different algorithms for deriving the same processing result from the same data. When an algorithm derives a processing result first, the processing result is used and the processing by the other algorithms is stopped or interrupted and updated to the same data which is reflected by the processing result data. This updated data is processed in parallel once again by a plurality of different algorithms, and when an algorithm derives another processing result first, the processing result is used, and the above processing is repeated, and inference. Consequently, sorting, data compression, simulation, and neurolearning can be processed at the highest possible speed.

Abstract: System Configuration files in source code are created from a high level definition of the distributed system which is to be integrated. The configuration files include data such as the types and formats of data for each process on each node of the system, identification of all applications and machine types, topography and the data manipulations needed for sending messages and files and the like from an application program in a first computer language and of a first data type to an application program in a second computer language and of a second data type. Node-specific data manipulation modules are formed at each node during start-up of the system, and these modules are automatically distributed to nodes on the network having the same architecture.

Abstract: Disclosed is an apparatus of synchronizing parallel processing among a plurality of processors including a plurality of synchronization units respectively corresponding to the plurality of processors and a control unit. The control unit and the synchronization units are connected in a loop. Each synchronization unit outputs a sync signal for informing that the synchronization unit has entered a wait state to an adjacent downstream unit. The control unit outputs a pulse for informing a completion of a synchronization among the processors to an uppermost-stream synchronization unit. The pulse is forwarded as far as an lowermost-stream synchronization unit.

Abstract: A semiconductor integrated circuit device includes a memory storing a microprogram used for controlling a desired function, a generator for generating an internal microprogram activating signal. A switching part selects either one of an external microprogram activating signal generated by an external device and the internal microprogram activating signal generated by the generator based on a first signal supplied from outside of the semiconductor integrated circuit device, thereby outputting a selected microprogram activating signal. A microaddress generator generates a microaddress of the microprogram stored in the memory. The microaddress generator is activated by the selected microprogram activating signal.

Abstract: An Ethernet circuit that combines the basic functionality of a twisted pair transceiver and a twisted pair/AUI encoder/decoder provides an autoswitching circuit that switches between a twisted pair data pathway and an AUI data pathway by changing from the twisted pair data pathway to the AUI data pathway when a link circuit fails to detect signals on the twisted pair medium and when the Ethernet circuit is not transmitting or executing a jabber procedure, and by changing from the AUI data pathway to the twisted pair data pathway when the link circuit detects signals on the twisted pair medium and when the Ethernet circuit is not transmitting or receiving.

Abstract: A program control circuit which comprises a register for holding the repetition number of a program operation to be repeated. The control circuit further comprises a counter for receiving the content of the register and adapted to be decremented in response to each execution of the program operation to be repeated. A memory stores a sequence of instructions. A controller transfers an instruction read from the memory without modification in a normal condition and modifies the instruction read from the memory into a no-operation instruction when the contents of the counter reaches a predetermined contents.

Abstract: A CMOS integrated circuit microcomputer is switchable under software control between high speed, high power operation and low speed, low power operation. The microcomputer includes asynchronous fast and slow clock oscillators. A synchronizing circuit coupled to the fast and slow clock oscillators receives a clock selection signal, and in response thereto produces a clock enable signal. The clock enable signal has the same frequency as and is synchronized with either the fast clock signal or the slow clock signal, depending on the state of the clock selection signal. The clock enable signal is input to gating circuitry that gates either the fast or the slow clock signal to provide a selectable speed clock signal to be used elsewhere in the microcomputer.

Abstract: A system (20) for producing an assignment of a plurality of entities (12) to a plurality of objects (16). This assignment is optimized subject to fixed constraints. The system (20) represents the assignment as a connectionist processing architecture having multiple processing elements (22), (24). These processing elements (22), (24) include a first class of processing elements (22) each representing groups of the entities (12) and a second class of processing elements (24) representing the objects (16). Also a plurality of interconnections (26) between the first and second classes of processing elements (22), (24) having variable weighted connection strengths which are a function of the constraints and also a function a random noise factor. The system (20) also includes a means for selectively assigning the entities (28) one-by-one to the object based on the strength of the interconnections (26).

Abstract: Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used.

Abstract: A dataflow machine for generally following data dependent path processes, the machine including an instruction store, an operand store, a plurality of data dependent path process executors, each process executor including an instruction queue and a queue loader associated with the instruction queue and operative to load the instruction queue with instructions selected from the instruction store, wherein the instructions with which the instruction queue is loaded are associated with a dynamically determined data dependent path process and are selected based, at least in part, on an active operand associated with each instruction, the active operand including a result of a previous instruction, and wherein at least some of the instructions are selected based, at least in part, on availability of an outside operand, and wherein the queue loader is operative to read the outside operand from the operand store, execution apparatus operative to sequentially apply each instruction in each instruction queue to at leas

Abstract: A universal processor-direct bus structure on a specifically partitioned motherboard uses a separate local bus translator card to adapt to a specific local bus protocol and configuration. The processor-direct bus on the motherboard contains a superset of all of the primary signals required to implement any desired local bus structure. The translator card incorporates the connectors and bus translation protocol for a specific local bus structure on a separate card which is connected to the partitioned motherboard through the universal processor-direct bus. Thus, the universal processor-direct bus combined with the translator card makes it possible to have a standard bus (for example an ISA (Industry Standard Architecture) bus, EISA bus, MCA bus, PCI bus, C-bus, S-100 bus and/or other buses) mounted directly on the motherboard with one or more of the same standard buses or a different local bus interfaced to the motherboard through the universal processor-direct bus.

Abstract: An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and address counter operating in a vector register mode, and register determining circuits for determining physical register numbers from the register numbers designated by an instruction in one of the two modes. Each register determining circuit has a first register determining circuit using an output of the window number modifier, for using the register file as a register window configuration, and a second register determining circuit using an output of the element counter, for using the register file as a vector register configuration. Physical registers of the register file are used as scalar registers in the register window mode, and used as vector registers in the vector register modes.

Abstract: A system for transferring digital signals between at least two printed circuit boards (packages) provided within a digital signal processing apparatus and each mounting a plurality of electronic parts such as microprocessors between a CPU package and a peripheral control package. The CPU package has a microprocessor (CPU), a transmitting sequential address generator 1, a receiving sequential address generator circuit 1, a transmitting dual port RAM 1 and a receiving dual port RAM 1. The peripheral control package has a digital processing circuit, a transmitting sequential address generator 2, a receiving sequential address generator 2, a transmitting dual port RAM 2 and a receiving dual port RAM. When a control information is to be sent from the CPU to the digital processing circuit, the CPU is required to only write the control information in the transmitting dual port RAM.

Abstract: A text document is stored as a sequence of primary records linked by a table. When an operator changes one of the records, the changed text is stored as a secondary record associated with a primary record in the table. If the operator later chooses to undo the changes, the secondary records are deleted. If he chooses to keep the changes, the secondary records are substituted for the associated primary records, and the latter are deleted.

Abstract: An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative cache memory including a data store section for storing lines of data from the system memory and a cache directory for indicating, by means of line identifier fields at any time, the lines of the system memory data currently resident in cache, is provided with a way to improve the distribution of data across the congruence classes within the cache. A mechanism is provided for performing a permutation operation on an M bit portion (X) of the system memory address, which permutation determines the congruence class into which the address will map. The permutation mechanism performs a bit-matrix multiplication of said M-bit address with an M.times.M matrix (where M is a real positive integer greater than 1) to produce a permuted M-bit address (X').

Abstract: In a word processing apparatus, the input characters can be printed in various printing forms such as an inclined character, a void character and a shadow character. The word processing apparatus properly divides the input character train into a plurality of subdivided character trains, and also designates the printing forms for these subdivided character trains. The housing of the word processing apparatus is manually swept across a print paper in contact thereto so as to print the characters. While the housing of the word processing apparatus is manually swept over a predetermined distance, one subdivided character train is printed out in the printing form in accordance with the designated printing form.

Abstract: A parallel computer has an operation request function and a plurality of processor elements. Each processor element has a sharable distributed memory for holding data, and is interconnected to a network to permit communication. Each processor element comprises a request sent unit for sending an operation request message for causing another processor element connected to a memory module to execute a recursive defining operation. The memory module stores data to be recursively defined. Each processor element further comprises an operation request execution element for accepting a message from another processor, temporarily stopping any other operation of the processor element in accordance with the content of the message, and executing the requested operation. Registers are also used for executing the operation requested by the other processor in addition to the general purpose registers and floating point registers.

Abstract: A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.