Abstract: Disclosed are package substrates and semiconductor packages including the same. A package substrate may have a plurality of corner regions; a core layer having a first surface and a second surface; an upper layer, which includes a plurality of first wiring structures and a plurality of first dielectric layers; and a lower layer, which includes a plurality of second wiring structures and a plurality of second dielectric layers. Additionally, an area proportion of top surfaces of the first wiring structures in the upper layer relative to a top surface of the upper layer on each of the corner regions is less than an area proportion of top surfaces of the second wiring structures in the lower layer relative to a top surface of the lower layer on each of the corner regions.

Abstract: In a method of producing a bonded wafer, the amount of depression of the polishing cloth is 50 ?m to 90 ?m, and the surface hardness (ASKER C) of the polishing cloth is 50 to 60. In the bonded wafer, the polycrystalline silicon layer has a thickness variation ?t of 5% or less, and the support substrate wafer has a GBIR of 0.2 ?m or less and an SFQR of 0.06 ?m or less after the polycrystalline silicon layer is polished.

Abstract: An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.

Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.

Abstract: A semiconductor device and method are provided whereby a series of spacers are formed in a first region and a second region of a substrate. The series of spacers in the first region are patterned while the series of spacers in the second region are protected in order to separate the properties of the spacers in the first region from the properties of the spacers in the second region.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.

Abstract: A semiconductor structure includes a first interconnect structure, a second interconnect structure, a molding, a first seal ring and a second seal ring. The molding surrounds the die. The molding and the die are disposed between the first interconnect structure and the second inter connect structure. The first seal ring is disposed in the first interconnect structure. The second seal ring is disposed in the second interconnect structure.

Abstract: Embodiments of the present disclosure provide a display panel, a method for manufacturing a display panel, and a display device. The display panel includes: a display substrate; an encapsulation layer covering the display substrate; a plurality of first electrodes on the encapsulation layer; a black matrix disposed on the encapsulation layer and covering the plurality of first electrodes; a plurality of color resist units disposed on the encapsulation layer and located in opening areas of the black matrix; and a plurality of second electrodes on the black matrix.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Abstract: A multi-voltage domain device includes a semiconductor layer including a first main surface, a second main surface arranged opposite to the first main surface, a first region including first circuitry that operates in a first voltage domain, a second region including second circuitry that operates in a second voltage domain different than the first voltage domain, and an isolation region that electrically isolates the first region from the second region in a lateral direction that extends parallel to the first and the second main surfaces. The isolation region includes at least one deep trench isolation barrier, each of which extends vertically from the first main surface to the second main surface. The multi-voltage domain device further includes at least one first capacitor configured to generate an electric field laterally across the isolation region between the first region and the second region.

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. A first layer is formed over a semiconductor layer, and a first patterned mask is formed over the first layer. A cyclic etch process is then performed to define a second patterned mask in the first layer. The cyclic etch process includes a first phase to form a polymer layer over the first patterned mask and a second phase to remove the polymer layer and to remove a portion of the first layer. A portion of the semiconductor layer is removed using the second patterned mask to define a fin from the semiconductor layer.

Abstract: Disclosed are a display panel and a display device. The display panel includes a substrate, a first electrode layer located on the substrate, a light emitting layer located on the first electrode layer, a second electrode layer located on the light emitting layer, an optical film layer located on the second electrode layer and configured to improve color offset and extracting light and an anti-reflecting layer located between the second electrode layer and the optical film layer; and the refractive index of the anti-reflecting layer is greater than that of the second electrode layer and is smaller than that of the optical film layer.

Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy along a lateral plane and across the substrate. The thermal energy is transferred along a non-lateral direction from the semiconductor device to the graphene layer using one or more thermal connectors.

Abstract: A method is presented for reducing capacitance coupling. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a source/drain epi for a first device, depositing a sacrificial material over the source/drain epi, forming a source/drain epi for a second device over the sacrificial material, and removing the sacrificial material to define an airgap directly between the source/drain epi for the first device and the source/drain epi for the second device.

Abstract: A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, wherein a contact layer of the resistive random access memory structure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structures may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first image sensor disposed within a first substrate and a second image sensor disposed within a second substrate. The second substrate has a first side facing the first substrate. The first side includes angled surfaces defining one or more recesses within the first side. A band-pass filter is arranged between the first substrate and the second substrate and is configured to reflect electromagnetic radiation that is within a first range of wavelengths.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having self-aligned isolations. In a non-limiting embodiment of the invention, a first gate stack is formed over channel regions of a first nanosheet stack. A second gate stack is formed over channel regions of a second nanosheet stack adjacent to the first nanosheet stack. An isolation pillar is positioned between the first gate stack and the second gate stack. The isolation pillar includes a top portion having a first width and a bottom portion having a second width less than the first width.