Abstract: An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.

Abstract: A display substrate, a method for manufacturing the display substrate, and a display device are provided in the present disclosure. The display substrate includes: a substrate; a first insulation layer on the substrate; a first signal line on a side of the first insulation layer distal to the substrate; a second insulation layer covering the first signal line; and a second signal line on a side of the second insulation layer distal to the substrate, the second signal line overlapping with the first signal line at an overlap region. A concave portion is formed in the first insulation layer. At least at the overlap region, the first signal line is in the concave portion.

Abstract: An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

Abstract: To provide an organic photoelectric conversion element, imaging device, and optical sensor having low dark currents, and a method of manufacturing a photoelectric conversion element. Provided is a photoelectric conversion element, including: a first electrode; an organic photoelectric conversion layer disposed in a layer upper than the first electrode, the organic photoelectric conversion layer including one or two or more organic semiconductor materials; a buffer layer disposed in a layer upper than the organic photoelectric conversion layer, the buffer layer including an amorphous inorganic material and having an energy level of 7.7 to 8.0 eV and a difference in a HOMO energy level from the organic photoelectric conversion layer of 2 eV or more; and a second electrode disposed in a layer upper than the buffer layer.

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

Abstract: An electronic package is formed by arranging two encapsulating portions of different materials between a plurality of electronic components stacked to each other to adjust a stress distribution of the electronic package, so that the degree of warpage of the electronic package can be optimally controlled.

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise laterally-outer longitudinal-edge portions and a respective laterally-inner portion laterally adjacent individual of the laterally-outer longitudinal-edge portions. The individual laterally-outer longitudinal-edge portions project upwardly and downwardly relative to its laterally-adjacent laterally-inner portion. Methods are disclosed.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

Abstract: In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.

Abstract: A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad provided on the PCB base, a semiconductor die provided on the conductive die pad, and a conductive die bonding agent that electrically connects the conductive die pad and the semiconductor die. The semiconductor module further includes a wire bonding pad provided on the PCB base, a wire that electrically connects the wire bonding pad and the semiconductor die, and a sealing resin that seals the conductive die pad, the semiconductor die, the conductive die bonding agent, the wire bonding pad, and the wire. In a planar view, the area of the conductive die pad is 5.0 mm2 or less.

Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

Abstract: An integrated circuit semiconductor device includes a first region including a first transistor and a second region in contact with the first region in a second direction. The first transistor includes a first active fin extending in a first direction, a first gate dielectric layer extending from the first active fin onto a first isolation layer in the second direction, and a first gate electrode on the first gate dielectric layer. The second region includes a second transistor including a second active fin extending in the first direction, a second gate dielectric layer extending from the second active fin onto a second isolation layer in the second direction, and a second gate electrode on the second gate dielectric layer. The integrated circuit semiconductor device includes a gate dielectric layer removal region proximate a boundary between the first region and the second region.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a source electrode over the oxide semiconductor film, a drain electrode over the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a second gate electrode over the second insulating film. The first insulating film includes a first opening. A connection electrode electrically connected to the first gate electrode through the first opening is formed over the first insulating film. The second insulating film includes a second opening that reaches the connection electrode. The second gate electrode includes an oxide conductive film and a metal film over the oxide conductive film. The connection electrode and the second gate electrode are electrically connected to each other through the metal film.

Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.

Abstract: In a general aspect, a semiconductor device can include a substrate and a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane. The device can also include a first negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The device can further include a second negative power supply terminal, laterally disposed from the positive power supply terminal and arranged in the first plane. The positive power supply terminal can be disposed between the first and second negative power supply terminals. The device can also include a conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge. A portion of the conductive bridge can be arranged in a second plane that is parallel to, and non-coplanar with the first plane.

Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.

Abstract: A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.