Abstract: Television signals from adjacent channels are broadcast with a common antenna. First television signals from a first channel are selected from a first frequency band including a plurality of channels. Second television signals from a second channel in the first frequency band are selected and wherein the second channel is adjacent to the first channel. The first and second signals are combined to provide a first combined signal and a second combined signal which are applied to a common antenna.

Abstract: The present invention relates to a television receiver for teletext for receiving a composite video signal having text information multiplex on a television video signal, and more particularly to a television receiver for teletext capable of displaying the television video signal and teletext screen simultaneously on the picture screen by superimposing or dividing the screen, and according to this television receiver for teletext, which comprises preprocessing means for issuing various preprocessing correction signals on the basis of the teletext signal extracted by the teletext signal receiving means, the preprocessing correction signal issued by the preprocessing means, and the teletext signal received by the teletext signal receiving means are combined and displayed on the picture screen, and thereby the boundary of the television video signal and teletext signal is clearer, so that the text of thetelet ext signal is easier to read.

Abstract: A digital television signal receiver includes a bin amplitude comparator for symbol decoding and match filtering to recover data synchronizing information from selected bin amplitude comparator responses generated during data slicing. The bin amplitude comparator concurrently supplies bin occupancy results for an amplitude slice including a value +S and for an amplitude slice including a value −S, which values +S and −S define the positive and negative excursions respectively of a binary data synchronization signal, current bin occupancy results being grouped together as two-parallel-bit serial input signal to a shift register clocked at symbol rate. Match filtering to detect data segment synchronization symbol code sequences is provided in accordance with an aspect of the invention by an AND gate supplied bits from selected storage locations in the shift register as wired input signals.

Abstract: A digital broadcast signal formed of compressed video data multiplexed with compressed audio data and program guide data is received. The signal is demultiplexed, and a display processor processes the program guide data so as to display a program guide window containing a number of program names. A cursor for designating a desired program is moved in the window and a controller controls the receiver so that a program designated by the cursor is received.

Abstract: A receiver for television signals is arranged to receive video signals comprising video data and information data. The receiver is arranged to respond to viewer operation of a control device (28). The receiver includes a processor (23) for processing selected information data to convert the same into signals representative thereof for output to a television in combination with the video signals. In one mode of operation the decoder responds to manipulation of the control device by causing brief scheduling information pertaining to programmes transmitted in the received signal to be displayed. In another mode of operation the receiver is arranged to display detailed scheduling information pertaining to plural different television signals. The receiver is operable to receive signals containing video data representing a plurality of video clips. The processor is arranged to process the signals and to cause simultaneous display of the clips on a television screen.

Abstract: A method for storing video frame data in a memory includes the steps of: sequentially receiving the video frame data; dividing the video frame data into a first part and a second part; storing the first part in the memory; storing the second part in the memory while the stored first part is read from the memory for a certain purpose; and reading the second part stored in the memory for the certain purpose.

Abstract: The data field synchronization segment as symbol coded for VSB transmission comprises pseudo-random noise (PN) sequence information that can be detected in a QAM/VSB DTV signal receiver using an envelope detector responsive to final intermediate-frequency signal and a match filter for responsive to the PN sequence information appearing in the envelope detector response. The envelope detector response to QAM transmission does not contain the PN sequence information detected by the match filter. A threshold detector is used for determining whether the match filter response is of sufficient energy to indicate occurrence in a received DTV signal of the PN sequence information in the data field synchronization segment of a VSB DTV transmission. Timed latch circuitry is used for latching the indication for a period of time longer than at least one DTV data field.

Abstract: Management of various audiovisual signal inputs to an entertainment system that includes a television receiver can be performed by a circuit in which a selector switch cyclically monitors the incoming signal inputs with video and audio signal detectors to register which inputs receive active signals. Selector switches for connecting an incoming audio signal and video signal to the television receiver are controlled by a central processing unit in response to the output of the detectors monitoring for active signal sources. Consequently, a user operating a user interface can most efficiently monitor and select active video and audio signal sources for use by the television set.

Abstract: A digital video encoder (16) receives a reference clock signal (REF_CLK27) for determining both a short term and a long term phase correction factor. A pulse detector (46) determines a number of sample clock (CLK324) time periods between the reference clock signal (REF_CLK27) and a clock signal (CLK27) that is derived from the data received by the digital video encoder (16). A phase increment generator (56) supplies an accumulator circuit (58) with a long term phase increment value based on the number of sample clocks and a TV_standard signal. A counter (60) and a phase look-up table (62) supply a short term increment value. The combined short term and long term increment values provide phase and frequency accuracy for the video subcarrier signal.

Abstract: Disclosed herein are a remote-controlled transmitter capable of properly and easily transferring information and an information transfer system using the remote-controlled transmitter. The remote-controlled transmitter is directed toward an information output apparatus and a capture button is operated in this state. A control code signal MB is outputted from a command generator and a remote-control signal RM is outputted from a signal output unit based on the control code signal MB. Based on the remote-control signal RM, information is outputted from the information output apparatus as a modulated sound SO. The sound SO is gathered by a microphone to obtain a signal Smic. The signal Smic is demodulated by a decoder and the demodulated signal is converted into a control code signal MS by a converter. The converted control code signal MS is stored in a memory.

Abstract: A method and apparatus for synchronizing audio and video streams in a video conferencing system is provided. During a video conferencing session, audio and video streams are transmitted from one processing system to a remote processing system, where they are recorded. Because the video stream has a variable frame rate during transmission, extra frames are inserted into the recorded video stream in order to maintain a constant, predetermined frame rate. During playback, synchronization information from the audio stream is provided by an audio playback process to a video playback process in order to synchronize the start of playing the audio and video streams, as well as to repeatedly synchronize the audio and video streams during playback.

Abstract: A digital television signal receiver includes a bin amplitude comparator for symbol decoding and match filtering to recover data synchronizing information from selected bin amplitude comparator responses generated during data slicing. The bin amplitude comparator concurrently supplies bin occupancy results for an amplitude slice including a value +S and for an amplitude slice including a value −S, which values +S and −S define the positive and negative excursions respectively of a binary data synchronization signal, current bin occupancy results being grouped together as two-parallel-bit serial input signal to a shift register clocked at symbol rate. Match filtering to detect data segment synchronization symbol code sequences is provided in accordance with an aspect of the invention by an AND gate supplied bits from selected storage locations in the shift register as wired input signals.

Abstract: A computer convergence system includes a convergence functionality module, a computer, and a display device. The convergence functionality module includes a first input for receiving a first video signal and a second input for receiving a second video signal. The computer is coupled to the convergence functionality module and receives therefrom indications of the first video signal received at the first input port and indications of said second video signal received at the second input port. The computer includes a controller for controlling the mapping of the indications of the first video signal to the primary video viewing surface, and further controls the mapping of the indications of the second video signal to either the second video viewing surface or the data acquisition destination.

Abstract: A video signal processing apparatus which can process video signals with different formats simply by switching between programs for processing video signals. Different system clock signals are sent to the input and output processes by employing a programmable signal processor 4, input synchronizing signal processor 8, programmable signal processor 6 and output synchronizing pulse processor 9. A method for processing the video signal can be flexibly changed simply by switching between signal processing programs for programmable signal processors. In addition, the use of a memory 5 enables the signal, which is processed using the system clock signal in the input process, to be processed using the system clock signal in the output process. The present invention thus allows the processing of video signals with many different signal formats. The design of efficient circuitry will greatly reduce costs and production processes.

Abstract: Dynamic adjustment techniques for aligning video images in cathode ray tube (CRT) devices are disclosed. A host computer stores correction factor data and video image data in video graphics controller RAM. The host computer processes and transmits the correction factor data, representative of the cathode ray tube distortion characteristics, to the CRT device during the retrace time of the electron beam and video image data during the trace time. The correction factor data may be generated by a vision system, a gain matrix table, interpolation engine or manual methods. Circuitry, within the CRT device, for separating the correction factor data from the video signal is disclosed along with the methods and apparatus used to decode correction data. Data can also be transferred from the monitor back to the host computer over the video connector.

Abstract: The signal processing apparatus for setting a vertical blanking signal of the television set that allows to set the beginning position and end position of a horizontal blanking signal irrespective of the numbers of lines in the vertical synchronous signal interval, comprising: an up counter for counting the vertical synchronous signal interval, synchronizing with the horizontal synchronous signal to lock forcedly the interlace signal to become a non-interlace signal; and a down counter for loading and down counting the count value of the up counter, wherein the down counter loads the data of the up counter immediately before the up counter is reset at a timing of the vertical synchronous signal and down counts the data which is loaded in the down counter as the initial value.

Abstract: A method and apparatus for performing phase detection and timing recovery for a vestigial sideband (VSB) signal by processing a complex valued passband VSB signal using a high order non-linearity to detect the phase of the VSB signal. As such, an all digital solution to timing recovery for a high definition television is provided.

Abstract: An image receiving unit receives a first image signal transmitted from a first image transmitting unit and a second image signal transmitted from a second image transmitting unit, synthesizes the first and second image signals, and displays them on the same display screen. The image receiving unit transmits information about display areas of the first and second image signals, i.e., image plane setting information, to each image transmitting unit. In accordance with the image plane setting information, each image transmitting unit reduces the data amount of a display area the first and second image signals are displayed in an overlap manner, prior to transmitting the first and second image signals. Also in accordance with the image plane setting information, each image transmitting unit processes the first or second image signals so as to match a display area thereof, prior to transmitting the first and second image signals.

Abstract: A detector circuit (1) for detecting the presence or absence of a television (2) on an output (3) of a video DAC (4) comprises a comparator (11) for comparing a voltage developed by the video signal on a control resistor R2 with a reference voltage of 0.5 volts. The resistor R2 is of 75 ohms and matches the internal impedance R1 of 75 ohms of the television (2). A latch (12) latches the output from the comparator (11) onto an output pin Q when the voltage developed across the control resistor R2 is developed by an equalisation pulse of the vertical blanking interval of the video signal. In the presence of a television (2) the voltage developed across the control resistor R2 is 0.35 volts, which pulls the output of the comparator (11) low, while in the absence of a television (2) the voltage developed across the control resistor R2 is 0.7 volts which pulls the output of the comparator (11) high.

Abstract: An audio/video production system facilitates professional quality image manipulation and editing using an enhanced general-purpose hardware. A program input may be translated into any of a variety of graphics or television formats, including NTSC, PAL, SECAM and HDTV, and stored as data-compressed images, using any of several commercially available methods such as Motion JPEG, MPEG, etc. While being processed, the images may be re-sized to produce a desired aspect ratio or dimensions using conventional techniques such as pixel interpolation. Frame rate conversion to and from conventional formats is performed by using the techniques employed for film-to-NTSC and film-to-PAL transfers, or by inter-frame interpolation, all well known in the art. By judicious selection of the optimal digitizing parameters, the system allows a user to establish an interrelated family of aspect ratios, resolutions, and frame rates, yet remain compatible with currently available and planned graphics and television formats.