Patents Examined by David J Goodwin
  • Patent number: 10437122
    Abstract: A display device, an array substrate, a pixel structure and a manufacturing method thereof are disclosed, and the pixel structure comprises a thin film transistor (101) and a first electrode (102) configured to form an electric field, the pixel structure further comprises a black matrix layer (103), and the black matrix layer (103) is located between the thin film transistor (101) and the first electrode (102). In the display device, the array substrate, the pixel structure and the manufacturing method, the black matrix layer is formed on the surface of the thin film transistor of the pixel structure, which simplifies the processes, saves materials, improves aperture ratio, and reduces parasitic capacitance between the common electrode and the data line to decrease the power consumption of the device.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 8, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Lijun Zhao
  • Patent number: 10431714
    Abstract: Engineered substrates for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a transducer structure having a plurality of semiconductor materials including a radiation-emitting active region. The device further includes an engineered substrate having a first material and a second material, at least one of the first material and the second material having a coefficient of thermal expansion at least approximately matched to a coefficient of thermal expansion of at least one of the plurality of semiconductor materials. At least one of the first material and the second material is positioned to receive radiation from the active region and modify a characteristic of the light.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: October 1, 2019
    Assignee: Qromis, Inc.
    Inventors: Martin F. Schubert, Cem Basceri, Vladimir Odnoblyudov, Casey Kurth, Thomas Gehrke
  • Patent number: 10418514
    Abstract: Exemplary embodiments of the present invention disclose a light emitting diode including an n-type contact layer doped with silicon, a p-type contact layer, an active region disposed between the n-type contact layer and the p-type contact layer, a superlattice layer disposed between the n-type contact layer and the active region, the superlattice layer including a plurality of layers, an undoped intermediate layer disposed between the superlattice layer and the n-type contact layer, and an electron reinforcing layer disposed between the undoped intermediate layer and the superlattice layer. Only a final layer of the superlattice layer closest to the active region is doped with silicon, and the silicon doping concentration of the final layer is higher than that of the n-type contact layer.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: September 17, 2019
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Kwang Joong Kim, Chang Suk Han, Kyung Hee Ye, Seung Kyu Choi, Ki Bum Nam, Nam Yoon Kim, Kyung Hae Kim, Ju Hyung Yoon
  • Patent number: 10418457
    Abstract: The structures and methods disclosed herein include changing composition of a metal alloy layer in an epitaxial electrode material to achieve tunable work functions for the electrode. In one example, the tunable work function is achieved using a layered structure, in which a crystalline rare earth oxide (REO) layer is epitaxially over a substrate or semiconductor, and a metal layer is over the crystalline REO layer. A semiconductor layer is thus in turn epitaxially grown over the metal layer, with a metal alloy layer over the semiconductor layer such that the ratio of constituents in the metal alloy is used to tune the work function of the metal layer.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 17, 2019
    Assignee: IQE plc
    Inventors: Rytis Dargis, Richard Hammond, Andrew Clark, Rodney Pelzel
  • Patent number: 10418524
    Abstract: An optoelectronic device comprises a substrate; a groove on the substrate; a plurality of semiconductor units on the substrate and separated by the groove, wherein each semiconductor unit comprises a first semiconductor layer, a second semiconductor layer, and an active region interposed between the first semiconductor layer and the second semiconductor layer; a connecting part crossing the groove for connecting two of the plurality of semiconductor units, wherein the connecting part comprises one end on the first semiconductor layer and another end on the second semiconductor layer; a first electrode comprising a plurality of first extensions jointly connected to the one end of the connecting part; and a second electrode comprising a plurality of second extensions jointly connected to the another end of the connecting part, wherein an amount of the plurality of first extensions is different from an amount of the plurality of second extensions.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 17, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chang-Huei Jing, Chien-Fu Shen
  • Patent number: 10411151
    Abstract: A stacked body is obtained by stacking a glass plate, a transparent resin sheet, a solar cell, a colored resin sheet, and a first resin sheet in the order. The stacked body is pressed under heat to fabricate the solar cell module. The module includes the glass plate, a transparent sealing layer placed between the glass plate and the solar cell and formed of the transparent resin sheet, a colored sealing layer placed between the first resin sheet and the solar cell and formed of the colored resin sheet, and the first resin sheet. One of the transparent resin sheet and the colored resin sheet has a tan ? of 1 or higher at a temperature of the pressing, and the other one of the transparent resin sheet and the colored resin sheet has a tan ? of less than 1 at the temperature of the pressing.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 10, 2019
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shintaro Saiki, Atsushi Saita
  • Patent number: 10388721
    Abstract: A capacitor structure is provided that includes conformal layers of a lower electrode, a high-k metal oxide dielectric, and an upper electrode. The capacitor structure is formed by a single process which enables the in-situ conformal deposition of the electrode and dielectric layers of the capacitor structure. The single process includes atomic layer deposition in which a metal-containing precursor is selected to provide each of the layers of the capacitor structure. The lower electrode layer is formed by utilizing the metal-containing precursor and a first reactive gas, the high-k metal oxide dielectric layer is provided by switching the first reactive gas to a second reactive gas, and the upper electrode layer is provided by switching the second reactive gas back to the first reactive gas.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10381380
    Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element.
    Type: Grant
    Filed: April 8, 2018
    Date of Patent: August 13, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • Patent number: 10354919
    Abstract: A method for dividing a wafer having a wiring layer including Cu on the front side, the front side of the wafer being partitioned by a plurality of crossing division lines to define a plurality of separate regions where a plurality of devices are formed. The method includes a laser processed groove forming step of applying a laser beam to the wiring layer along each division line to thereby remove the wiring layer along each division line and form a laser processed groove along each division line, a cutting step of using a cutting blade having a thickness smaller than the width of each laser processed groove to fully cut the wafer along each laser processed groove after performing the laser processed groove forming step, and a dry etching step of dry-etching at least each laser processed groove after performing the laser processed groove forming step.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: July 16, 2019
    Assignee: DISCO CORPORATION
    Inventors: Tomotaka Tabuchi, Kentaro Odanaka, Satoshi Kumazawa, Senichi Ryo, Yuki Ogawa
  • Patent number: 10355018
    Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, David Daycock, Kunal R. Parekh, Martin C. Roberts, Yushi Hu
  • Patent number: 10354971
    Abstract: The invention concerns a method for producing a chip module having a carrier substrate and at least one chip arranged on the carrier substrate, as well as a contact conductor arrangement for connecting chip pads to contacts arranged on a contact face of the chip module, in which method the front face of the chip which is provided with the chip pads is secured to the carrier substrate and then the contact conductor arrangement is formed by structuring of a contact material layer of the carrier substrate.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 16, 2019
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventors: Ghassem Azdasht, Thorsten Teutsch, Ricardo Geelhaar
  • Patent number: 10347752
    Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
  • Patent number: 10347823
    Abstract: A magnetoresistive element includes a channel layer, a first ferromagnetic layer, a second ferromagnetic layer, and a reference electrode. The first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode are apart from each other and are electrically connected to each other through the channel layer. The average resistivity of a sixth region composed of a first region, a second region, and a fourth region is higher than the average resistivity of a seventh region composed of the second region, a third region, and a fifth region.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: July 9, 2019
    Assignee: TDK CORPORATION
    Inventor: Hayato Koike
  • Patent number: 10347614
    Abstract: Solid state transducers with state detection, and associated systems and methods are disclosed. A solid state transducer system in accordance with a particular embodiment includes a support substrate and a solid state emitter carried by the support substrate. The solid state emitter can include a first semiconductor component, a second semiconductor component, and an active region between the first and second semiconductor components. The system can further include a state device carried by the support substrate and positioned to detect a state of the solid state emitter and/or an electrical path of which the solid state emitter forms a part. The state device can be formed from at least one state-sensing component having a composition different than that of the first semiconductor component, the second semiconductor component, and the active region. The state device and the solid state emitter can be stacked along a common axis.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 10340285
    Abstract: According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Ishida, Yoshiaki Fukuzumi, Takayuki Okada, Masaki Tsuji
  • Patent number: 10325882
    Abstract: A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-woo Kang, Byung-lyul Park, Kyoung-hwan Kim, Kun-sang Park, Young-gyu Ahn
  • Patent number: 10283584
    Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Ignasi Cortes Mayol, Tom Herrmann, Andrei Sidelnicov, El Mehdi Bazizi
  • Patent number: 10278290
    Abstract: An electronic component embedded substrate 1 includes a substrate 10 having a wiring layer 11 and an insulating layer 12; an electronic component 20 built in the substrate 10, and having a pair of electrode layers 21A and 21B, and a dielectric layer 22; and a stress relieving layer 30 provided closer to the wiring layer 11 than the insulating layer 12 is in the lamination direction, wherein at least part of an end portion of the electronic component 20 on the wiring layer 11 side is in contact with the stress relieving layer 30, wherein at least part of an end portion of the electronic component 20 on the insulating layer 12 side is in contact with the insulating layer 12, and wherein the Young's modulus of the stress relieving layer 30 is lower than the Young's modulus of the electrode layer 21B.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: TDK CORPORATION
    Inventors: Kenichi Yoshida, Mitsuhiro Tomikawa
  • Patent number: 10276528
    Abstract: A semiconductor device and a manufacturing method for the semiconductor device are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump a spacer and surrounds the bump and disposed between the etching stop layer and the bump.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Cheng-Lung Yang, Chen-Shien Chen, Hon-Lin Huang, Chao-Yi Wang, Ching-Hui Chen, Chien-Hung Kuo
  • Patent number: 10269974
    Abstract: The present invention discloses a method of manufacturing array substrate, comprising: A) defining a heavily doped region and a lightly doped region of a source electrode of an N-channel area, and a heavily doped region and a lightly doped region of a drain electrode of the N-channel area by using a first photomask having a first pattern; B) defining a doped region of a source electrode of a P-channel area and a doped region of a drain electrode of the P-channel area by using a second photomask having a second pattern; C) defining a pixel region, a contact hole region by using a third photomask having a third pattern; and D) defining a metal electrode region by using a fourth photomask having a fourth pattern.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 23, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Macai Lu