Abstract: A semiconductor device is manufactured by implanting impurity ions in one surface of a semiconductor substrate made of silicon carbide; irradiating a region of the semiconductor substrate implanted with the impurity ions with laser light of a wavelength in the ultraviolet region; and forming, on a surface of a high-concentration impurity layer formed by irradiating with the laser light, an electrode made of metal in ohmic contact with the high-concentration impurity layer. When irradiating with the laser light, a first concentration peak of the impurity ions that exceeds a solubility limit concentration of the impurity ions in silicon carbide is formed in a surface region near the one surface of the semiconductor substrate within the high-concentration impurity layer.

Abstract: The present disclosure describes solution methods for manufacturing perovskite halide films for use in solar cells. The methods include the use of additives that facilitate the formation of transitory, intermediate films that are later transformed into the final target perovskite halide films, such that the final films provide improved physical characteristics and operational performance.

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

Abstract: A display panel comprises: an array substrate comprising a display area and a trace area located around the display area; a light-emitting layer located in the display area and electrically connected to a first side of the array substrate; a fanout circuit located in the trace area; a fanout circuit base layer disposed between the fanout circuit and the array substrate; and a driver chip located at a second side of the array substrate; wherein the fanout circuit and the fanout circuit base layer are bent from the first side to the second side along a sidewall of the array substrate, the fanout circuit is electrically connected to the array substrate at the first side, and the fanout circuit is electrically connected to the driver chip at the second side.

Abstract: Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.

Abstract: A method for manufacturing a light emitting device includes: a substrate preparation step for preparing a substrate having a first region on which a plurality of light emitting devices are formed, and a second region surrounding the first region; a reinforcing member forming step for forming a reinforcing member by applying a resin material on the second region and hardening the resin material; a mounting step for mounting a plurality of light emitting elements on the first region; a light-transmissive member placing step for forming a plurality of light-transmissive members respectively on the light emitting elements; a sealing member forming step for sealing the plurality of light emitting elements and the plurality of light-transmissive members using a sealing member; and a cutting step for cutting the substrate and the sealing member and separating into individual light emitting devices.

Abstract: A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

Abstract: A method for forming a light-sensing device is provided. The method includes forming a light-sensing region in a semiconductor substrate. The semiconductor substrate has a front surface and a light-receiving surface opposite to the front surface. The method also includes forming a first dielectric layer over the front surface and forming a second dielectric layer over the first dielectric layer. The second dielectric layer has a different refractive index than that of the first dielectric layer, and the first dielectric layer and the second dielectric layer together form a (or a part of a) light-reflective element. The method further includes partially removing the first dielectric layer and the second dielectric layer to form a contact opening. In addition, the method includes forming a conductive contact to partially (or completely) fill the contact opening.

Abstract: A method for producing an organic EL display device in an embodiment includes step (a) of forming a polymer film (14) on a support substrate (12); step (b) of forming a plurality of organic EL display panel portions (20) on the polymer film (14); and step (c) of causing the organic EL display panel portions (20) on a stage (200S) to face the stage (200S), and directing a line beam (100L) in a direction from the support substrate (12) toward at least an interface between the polymer film (14) and the support substrate (12) while moving the line beam (100L) and the support substrate (12) with respect to each other, the step (c) being performed in a state where the organic EL display panel portions (20) are substantially thermally insulated from the stage (200S).

Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes forming a slit in a first wafer in which a first semiconductor layer is formed on a first substrate, sticking together the first wafer in which the slit is formed and a second wafer in which a second semiconductor layer is formed on a second substrate, the sticking being performed between a side of the first semiconductor layer and a side of the second semiconductor layer, thinning the first substrate or the second substrate of a member obtained by the sticking, forming an interconnection on a face of the substrate that is thinned, and dicing a member on which the interconnection is formed in accordance with a position of the slit.

Abstract: A light-emitting diode includes a transparent substrate with a first surface, a second surface opposite to the first surface, and a side surface connected to the first surface and the second surface; a first light-emitting structure; a second light-emitting structure; a connecting layer, connected to the first light-emitting structure and the second light-emitting structure; a circuit arranged between the transparent substrate and the first light-emitting structure, and having a portion formed on the first surface without extending to the second surface; and a structure with diffusers, covering the first light-emitting structure and the second light-emitting structure on the first surface without crossing over the side surface.

Abstract: A method of forming a semiconductor device includes following steps. Firstly, a substrate is provided and the substrate has a first semiconductor layer formed thereon. Next, an isolating structure is formed in the first semiconductor layer, and a sacrificial layer is formed on the first semiconductor layer by consuming a top portion of the first semiconductor layer. Then, the sacrificial layer is removed to form a second semiconductor layer, and a portion of the isolating structure is also removed to form a shallow trench isolation (STI), with a top surface of the shallow trench isolation being substantially coplanar with a top surface of the second semiconductor layer.

Abstract: Semiconductor devices are provided. The semiconductor device includes a first dielectric layer, a bump, an etching stop layer and a spacer. The first dielectric layer is disposed over and exposes a conductive structure. The bump is partially disposed in the first dielectric layer to electrically connect the conductive structure. The etching stop layer is disposed over the first dielectric layer aside the bump. The spacer surrounds the bump and disposed between the etching stop layer and the bump.

Abstract: An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

Abstract: Disclosed are methods of forming a CMOS device. One non-limiting method may include providing a gate structure atop a substrate, and forming a first spacer over the gate structure. The method may include removing the first spacer from just an upper portion of the gate structure by performing an angled reactive ion etch or angled implantation disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include forming a second spacer over the upper portion of the gate structure and the first spacer along a lower portion of the gate structure. A thickness of the first spacer and the second spacer along the lower portion of the gate structure may be greater than a thickness of the second spacer along the upper portion of the gate structure.

Abstract: The TFT array substrate has a third conductive layer connected to a first conductive layer and a second conductive layer through a first via and a second via, respectively. The third conductive layer further has separated first and second openings. The first opening has a vertical projection to a side of the second via and has an end extending beyond an edge of the second via adjacent to the first via. The second opening has a vertical projection to a side of the first via and has an end extending beyond an edge of the first via adjacent to the second via. As such, when the third conductive layer is stricken by static electricity, the first and second openings prevent a crack from breaking the first and second conductive layers apart, thereby enhancing the reliability of the connection between the first and second conductive layers.

Abstract: A method of manufacturing a memory device includes forming a transistor on a substrate, forming a lower interlayer insulating layer covering the transistor, forming a hydrogen supply layer on the lower interlayer insulating layer, forming a hydrogen blocking layer on the hydrogen supply layer, annealing the transistor, the lower interlayer insulating layer, and the hydrogen supply layer, forming a memory cell on the hydrogen blocking layer after the annealing, and forming an upper interlayer insulating layer surrounding the memory cell and having a third average hydrogen concentration less than the second average hydrogen concentration.

Abstract: A poly-silicon layer and a method of manufacturing the same, methods of manufacturing a thin film transistor, and an array substrate are provided. The method of manufacturing the poly-silicon layer includes forming an amorphous silicon layer, crystallizing the amorphous silicon layer to form a first poly-silicon layer, and processing the first poly-silicon layer to form a second poly-silicon layer using a green laser annealing process.

Abstract: An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.