Patents Examined by David Lam
  • Patent number: 10482969
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data and a memory die comprising a plurality of non-volatile memory cells. Here, the memory die receives the threshold number of bit flips from the non-volatile storage controller, programs data to a set of the non-volatile memory cells over a first number of program loop cycles, and programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: November 19, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Refael Ben-Rubi
  • Patent number: 10475493
    Abstract: This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 12, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Manabu Sakai, Qui Vi Nguyen, Yen-Lung Li
  • Patent number: 10475488
    Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Vijayakrishna J. Vankayala
  • Patent number: 10475490
    Abstract: A memory device includes memory cells and a refresh module. The memory cells are coupled to a bit line, in which at least one memory cell of the memory cells is configured to store predetermined data. The refresh module is configured to refresh the at least one memory cell if a target memory cell of the memory cells is programmed or erased, in order to keep at least one cell current of the at least one memory cell away from a predetermined verify current level.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yue-Der Chih, Cheng-Hsiung Kuo, Gu-Huan Li, Chien-Yin Liu
  • Patent number: 10460779
    Abstract: An apparatus has a reference magnetic tunnel junction with a high aspect ratio including a reference layer with magnetization along a minor axis and a storage layer with magnetization along a major axis. The storage layer magnetization is substantially perpendicular to the magnetization along the minor axis. The magnetization orientation between the minor axis and the major axis is maintained by shape anisotropy caused by the high aspect ratio.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: October 29, 2019
    Assignee: CROCUS TECHNOLOGY INC.
    Inventors: Michael Gaidis, Thao Tran
  • Patent number: 10460813
    Abstract: A nonvolatile memory device according to some embodiments of the inventive concepts may include a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second page buffer connected to the memory cell array via a second plurality of bit lines. The first page buffer circuit may include a first bit line selection circuit, a first bit line shut-off circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line shut-off circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line shut-off circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. A width of the data lines may be greater than a width of the bit lines.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeung-hwan Park
  • Patent number: 10453896
    Abstract: A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4F2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: October 22, 2019
    Assignee: Crossbar, Inc.
    Inventors: Hagop Nazarian, Harry Yue Gee
  • Patent number: 10446201
    Abstract: According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sumeer Goel, Prashant Kenkare
  • Patent number: 10438685
    Abstract: A memory device includes a first fail address register that stores a fail address, an input address register that stores an input address, a data comparison circuit that compares write data to be stored in a memory cell corresponding to the input address with read data read from the memory cell, an address comparison circuit that compares the fail address and the input address, and a second fail address register that stores bits of the fail address in parallel based on a first comparison result of the write data with the read data and a second comparison result of the fail address with the input address.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyungkyu Kim, Sang-Hoon Jung
  • Patent number: 10431320
    Abstract: A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-Shin Kwon, Jong-Hyoung Lim, Chang-Soo Lee, Chung-Ki Lee
  • Patent number: 10424386
    Abstract: An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors is illustrated. Whether the memory block or the memory sector corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal is verified, wherein the sector enable signal is determined according to whether the memory block has at least one over-erased transistor memory cell. The transistor memory cells of the memory block or the memory sector will be erased according to the sector enable signal if the memory block or the memory sector corresponding to the address that has the under-erased transistor memory cell.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: September 24, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Chih-Hao Chen
  • Patent number: 10424368
    Abstract: Apparatuses and methods for concentrated arrangement of amplifiers. An example apparatus may include a first amplifier circuit including a first and second transistors. The first width different from the second width, the first length different from the second length. The apparatus further including a second amplifier circuit including a third and fourth transistors. The first transistor including a first gate electrode and the third transistor having a third gate electrode each having a first length and a first, diffusion region and a third diffusion region, respectively, each having a first width, and the second transistor including a second gate electrode and the fourth transistor having a fourth gate electrode each with a fourth length and a second diffusion region and a fourth diffusion region, respectively, each having a second width. The first and third transistors are collectively arranged and the second and fourth transistors are collectively arranged.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yoshiaki Shimizu
  • Patent number: 10423531
    Abstract: Subject matter disclosed herein relates to techniques to read memory in a continuous fashion.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yihua Zhang, Jun Shen
  • Patent number: 10424355
    Abstract: A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are vertically stacked, wherein the first semiconductor chip includes a first column data driving circuit configured to transmit internal data to the second semiconductor chip in a DDR (double data rate) scheme based on an internal strobe signal, and a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Dong-Uk Lee, Young-Ju Kim, Keun-Soo Song
  • Patent number: 10410684
    Abstract: The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: September 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Ting-Hao Chang, Ching-Cheng Lung, Yu-Tse Kuo, Shih-Hao Liang, Chun-Hsien Huang, Shu-Ru Wang, Hsin-Chih Yu
  • Patent number: 10403348
    Abstract: Disclosed is a non-destructive large current-readout ferroelectric single-crystal thin film memory as well as a method of preparing the ferroelectric memory and a method of operating the ferroelectric memory. The large current-readout ferroelectric single-crystal thin film memory comprises a ferroelectric storage layer, which is a ferroelectric single-crystal storage layer. The non-destructive readout ferroelectric memory has a greatly increased read current in an on-state, and moreover, the data retention performance and data endurance performance are improved.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: September 3, 2019
    Assignee: Fudan University
    Inventors: Anquan Jiang, Wenping Geng
  • Patent number: 10403753
    Abstract: The invention relates to heterostructures including a layer of a two-dimensional material placed on a multiferroic layer. An ordered array of differing polarization domains and surface charges in the multiferroic layer produces corresponding domains having differing properties in the two-dimensional material. When the multiferroic layer is ferroelectric, the ferroelectric polarization domains in the layer produce local electric fields that penetrate the two-dimensional material. The local electric fields and surface charges can control the structural phase of the two-dimensional material, which in turn determines whether the two-dimensional material layer is insulating or metallic, has a band gap or no band gap, and whether it is magnetic or non-magnetic. Methods for producing the heterostructures are provided. Devices incorporating the heterostructures are also provided.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 3, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Berend T. Jonker, Connie H. Li, Kathleen M. McCreary
  • Patent number: 10381089
    Abstract: A semiconductor apparatus comprising: a memory device including at least a word line; and a controller suitable for controlling the memory device to perform a write operation and a read operation, wherein the controller includes a counting unit suitable for counting a number of memory cells coupled to the word line for respective threshold voltages, and wherein the controller controls the memory device to perform a read operation based on the counted number of memory cells for the respective threshold voltages.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventor: Woo-Hyun Kim
  • Patent number: 10381068
    Abstract: Ultra dense and stable 4T SRAM designs are provided. In one aspect, a 4T SRAM bitcell includes: two NFETs cross-coupled with two PFETs, wherein the NFETs are both connected directly to a word line, wherein a first one of the PFETs is connected to a first bit line via a first one of the NFETs and a second one of the PFETs is connected to a second bit line via a second one of the NFETs, and wherein the PFETs are each separately connected to ground. An SRAM device including the present 4T SRAM bitcell as well as a method of operating the SRAM device are also provided.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Myung-Hee Na, Robert Wong, Jens Haetty, Sean Burns
  • Patent number: 10373655
    Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Asaki, Shuichi Tsukada, Sachiko Edo