Patents Examined by David Lam
  • Patent number: 10896703
    Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Smith, Vijayakrishna J. Vankayala
  • Patent number: 10896709
    Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 19, 2021
    Inventor: Artur Antonyan
  • Patent number: 10896714
    Abstract: Methods, systems, and devices for access line disturbance mitigation are described to, for example, reduce voltage disturbances on deselected digit lines during a read or write operation. Memory cells of a memory device may be couplable with a write circuit including a level shifter circuit, such that changes in voltage on a selected digit line may be controlled via a level shifter circuit of a write circuit associated with a selected memory cell. The write circuit may write a logic state to the memory cell after completing a read operation. One or more write voltages may be applied to or removed from the memory cell via the level shifter circuit, which may control a slew rate of one or more voltage changes on the selected digit line. The slew rate(s) may be controlled via a current driver circuit coupled with a pull-up circuit or a pull-down circuit of the level shifter circuit.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Xinwei Guo
  • Patent number: 10892011
    Abstract: A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC c
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 12, 2021
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 10891995
    Abstract: A semiconductor device and command generation method, the semiconductor device includes a command recovery circuit configured to receive a command from a plurality of commands, to store a code signal which is generated by encoding the received command from the plurality of commands, depending on the received command, and generate a plurality of internal commands by decoding a command code signal which is generated from the code signal after shifting the received command depending on a shifting control signal; and a memory circuit configured to perform an internal operation depending on the plurality of internal commands.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Seung Wook Oh, Jin Il Chung
  • Patent number: 10885947
    Abstract: A power gating system including: a first power line coupled to a first pad; a second power line coupled to a second pad; a third power line coupled to a plurality of logic gates in common; a first power gating switch coupled between the first and third power lines; and a second power gating switch coupled between the second and third power lines. When a double power mode is set, the first and second power gating switches may be turned on to couple the first and second power lines to the third power line at the same time.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10878902
    Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-An Lai, Chung-Cheng Chou, Yu-Der Chih
  • Patent number: 10872666
    Abstract: Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Richard E. Fackenthal
  • Patent number: 10872660
    Abstract: In one embodiment, systems, methods, and apparatus are described that can reduce the peak current through semiconductor memory devices such as RRAM devices. In one embodiment, transition metal dichalcogenide (TMD) materials can be used to in connection with both the transistors and the memory (for example, RRAM) devices. In one embodiment, two-dimensional (2D) materials, that is, materials that are on the order of a few angstroms thick can be used in connection with both the transistors and the memory (for example, RRAM) devices. In one embodiment, the TMD layer(s) and/or the 2D material(s) can act as a ballast to the RRAM device that can control the current flow through the RRAM device. In one embodiment, the systems, methods, and apparatus can serve to reduce the current as the voltage increases at a predetermined range, a property that can be referred to as negative differential resistance (NDR).
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 22, 2020
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Ravi Pillarisetty, Van H. Le, Gilbert Dewey
  • Patent number: 10861562
    Abstract: Techniques related to improving a performance related to at least data reads from a memory are described. In an example, a computer system hosts a regression model that includes a neural network. The neural network is trained based on training data that is measured under different combinations of operational conditions and storage conditions. In operation, actual operational and storage conditions associated with the memory are input to the regression model. The neural network outputs a voltage read threshold based on these actual conditions. The computer system uses the voltage read threshold to read data stored in the memory.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 8, 2020
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Xuanxuan Lu, Meysam Asadi, Jianqing Chen
  • Patent number: 10855486
    Abstract: Embodiments of the present invention provide a method and system for dynamically controlling an appliance based on information received from a wearable device, to regulate the user's health. A wearable device is identified and configured to monitor at least one physiological aspect of the user. A controllable appliance with at least one sensor and at least one controllable setting is also identified. Health information of the user is received and utilized in generating, a user profile which comprises parameters related to the health of the user. Data from the wearable device and date from the controllable appliance is analyzed and it is determined whether the data matches the parameters related to the health of the user. If the data does not match the parameters related to the health of the user, then at least one controllable setting of the at least one controllable appliance is adjusted.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: December 1, 2020
    Assignee: ECOBEE INC.
    Inventors: Sandeep Bazar, Kaustubh I. Katruwar, Sandeep R. Patil, Sachin C. Punadikar
  • Patent number: 10854243
    Abstract: Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 1, 2020
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, X. M. Henry Huang, Thomas Rueckes, Ramesh A. Sivarajan
  • Patent number: 10854285
    Abstract: A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Hsiao-Te Chang, Wen-Long Wang
  • Patent number: 10847206
    Abstract: A semiconductor device includes a shifted write signal generation circuit, a shifted address generation circuit and a bank address latch circuit. The shifted write signal generation circuit is configured to shift a write signal based on a mode signal to generate a shifted write signal. The shifted address generation circuit is configured to shift an internal address based on the mode signal to generate a shifted internal address. The bank address latch circuit is configured to latch and store the internal address based on the write signal, configured to latch and store the shifted internal address based on the shifted write signal, and configured to generate a write bank address from the stored internal address and the stored address of the shifted internal address.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10847198
    Abstract: A magnetic data recording system utilizing different magnetic memory element types to optimize competing performance parameters in a common memory chip. The memory system includes a first memory portion which can be a main memory and which includes magnetic memory elements of a first type, and a second memory region which can be a temporary memory region and which includes magnetic memory elements of a second type. A memory controller can be provided for controlling the input and retrieval of data to and from the first and second memory elements. The second, memory region can be a scratchpad memory or could also be cache type memory. The first type of magnetic memory elements can be designed for high data retention, whereas the second type of magnetic memory elements can be designed for fast write speed (low latency) and low write power consumption.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: November 24, 2020
    Assignee: SPIN MEMORY, INC.
    Inventors: Kadriye Deniz Bozdag, Eric Michael Ryan, Kuk-Hwan Kim
  • Patent number: 10847579
    Abstract: A logical NAND memory architecture comprising two-terminal, non-volatile resistive memory is disclosed. By way of example, disclosed logical NAND architectures can comprise non-volatile memory cells having approximately 4 F2 area. This facilitates very high memory densities, even for advanced technology nodes. Further, the disclosed architectures are CMOS compatible, and can be constructed among back-end-of-line (BEOL) metal layers of an integrated chip. In some embodiments, subsets of two-terminal memory cells in a NAND array can be constructed between different pairs of BEOL metal layers. In other embodiments, the two-terminal memory cells can be constructed between a single pair of BEOL metal layers.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 24, 2020
    Assignee: Crossbar, Inc.
    Inventors: Hagop Nazarian, Harry Yue Gee
  • Patent number: 10839902
    Abstract: A method for programming a non-volatile resistive memory including a plurality of non-volatile resistive memory cells, each memory cell being able to switch in a reversible manner between a low resistance state in which the memory cell has an electrical resistance value lower than a first resistance threshold; and a high resistance state in which the memory cell has an electrical resistance value greater than the first resistance threshold; the programming method including determining the first resistance threshold carried out periodically during the lifetime of the resistive memory.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 17, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Alessandro Grossi, Elisa Vianello
  • Patent number: 10840383
    Abstract: Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 17, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Qingqing Liang, Peter Graeme Clarke, George Pete Imthurn, Sinan Goktepeli, Sivakumar Kumarasamy
  • Patent number: 10839869
    Abstract: A multi-level sensing circuit for a multi-level memory device configured to “recognize” more than two different voltages. The multi-level voltage sensing circuit may include a pre-charge controller configured to pre-charge a pair of bit lines with a bit-line pre-charge voltage level in response to an equalizing signal during a sensing mode. The multi-level voltage sensing circuit may include a read controller configured to maintain a voltage of the pair of bit lines at the bit-line pre-charge voltage level in response to a read control signal during a sensing operation. The multi-level voltage sensing circuit may include a sense-amplifier configured to generate data of the pair of bit lines during the sensing mode. The multi-level voltage sensing circuit may include a voltage sensor configured to generate the equalizing signal by comparing a bit-line voltage with a reference voltage.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Tae Hun Kim
  • Patent number: 10839875
    Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 17, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srinivas R. Sathu, John Wuu, Russell Schreiber, Martin Piorkowski