Abstract: A method for performing access control regarding quality of service (QoS) optimization of a memory device with aid of machine learning an associated apparatus (e.g. the memory device and a controller thereof) are provided. The method may include: performing background scan on the NV memory to collect valley information of voltage distribution of memory cells within the NV memory, and performing machine learning based on a reinforcement learning model according to the valley information, in order to prepare a plurality of tables through the machine learning based on the reinforcement learning model in advance, for use of reading data from the NV memory; during a first time interval, writing first data and read the first data using a first table within the plurality of tables; and during a second time interval, reading the first data using a second table within the plurality of tables.

Abstract: A post package repair (PPR) method is disclosed. The PPR method includes the following operations: receiving a first PPR signal and a second PPR signal, in which the first PPR signal corresponds to a first PPR mode, and the second PPR signal corresponds to a second PPR mode; generating a first valid signal and a second valid signal according to the first PPR signal and the second PPR signal, in which only one of the first valid signal and the second valid signal comprises a valid information when both of the first PPR signal and the second PPR signal comprise an enabled information; in which when the first valid signal comprises the valid information, the first PPR mode is executed, and when the second valid signal comprises the valid information, the second PPR mode is executed.

Abstract: An apparatus is described. The apparatus according to an embodiment includes a voltage dividing resistor circuit formed on a semiconductor substrate and including first and second resistors and first and second selector switches. The first and second resistors and the first and second selector switches are arranged with one of first and second layouts. The first layout is such that the first and second selector switches are placed between the first and second resistors. The second layout is such that the first and second resistors are placed between the first and second selector switches.

Abstract: A semiconductor device includes a first command pulse generation circuit configured to generate a first command pulse from an internal command address based on a first blocking signal; and a second command pulse generation circuit configured to generate a second command pulse from the internal command address based on a second blocking signal.

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.

Abstract: A non-volatile memory device includes a non-volatile memory cell array, an input/output pad unit, and a peripheral circuit. The non-volatile memory device executes an operation requested by a controller. The input/output pad component provides a path through which a command and data related to the operation requested by the controller are input to the non-volatile memory device, and through which a result of execution of the requested operation is output to the controller. The peripheral circuit is configured to be loaded with a plurality of commands provided by the controller, to temporarily store program data provided by the controller to be written in the non-volatile memory cell array and data read from the non-volatile memory cell array, to adjust an execution order of the commands asynchronously with the controller based on an internal operation status of the non-volatile memory device, and to execute the commands in the adjusted execution order.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: A computerized component, designed to be used in a vehicle, is able to detect an ambient environmental variable; determine a memory profile corresponding to the ambient environmental variable; access memory parameters from the memory profile; and configure memory of the computerized component based on the accessed memory parameters. Another computerized component may be used to detect that the computerized component is initiating a shutdown procedure; obtain an ambient environmental variable, the ambient environmental variable indicating a state of an operating environment of the computerized component; identify memory parameters of random access memory integrated with the computerized component; and write the memory parameters to a memory profile stored in non-volatile storage in the computerized component, the memory profile keyed to the ambient environmental variable.

Abstract: Various embodiments comprise apparatuses and methods of forming the apparatuses. In one embodiment, an exemplary apparatus includes a plurality of memory cells. At least a portion of the memory cells have a bottom electrode with each bottom electrode being at least partially electrically isolated from remaining ones of the bottom electrodes. At least one resistive interconnect electrically couples two or more of the bottom electrodes. The resistive interconnect is arranged to discharge at least a portion of excess charge from the two or more bottom electrodes. Additional apparatuses and methods of forming the apparatuses are disclosed.

Abstract: A magnetoresistive random access memory (MRAM) memory cell comprises a pinned layer having fixed direction of magnetization that is perpendicular to a plane of the pinned layer, a first free layer having a direction of magnetization that can be switched and is perpendicular to a plane of the first free layer, a tunnel barrier positioned between the pinned layer and the first free layer, a second free layer having a direction of magnetization that can be switched, and a spacer layer positioned between the first free layer and the second free layer. Temperature dependence of coercivity of the second free layer is greater than temperature dependence of coercivity of the first free layer.

Abstract: A device for providing gated data signals includes a delay path configured to receive an input signal and output the input signal that is delayed from the input signal by a time interval; a gating signal generator configured to supply a gating signal; a gating circuit configured to receive the data signal from the delay path at the data input, receive the gating signal at the gating input, and output at the data output an output signal indicative of the received data signal when the gating signal is present at the gating input; and a delay controller configured to receive a variable delay control signal and set the delay time interval according to the delay control signal.

Abstract: According to one embodiment, a magnetic device includes a first memory cell including a magnetoresistive effect element, a selector, and a first barrier material disposed between the selector and the magnetoresistive effect element, wherein the first barrier material has a thermal conductivity of 5 W/mK or lower.

Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

Abstract: An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

Abstract: A memory device includes a first sense amplifier, and a second sense amplifier. During a read operation, a first signal based on a first output of the first sense amplifier corresponding to data stored in a memory cell before writing reference data therein and a second signal based on a second output of the first sense amplifier corresponding to data stored in the memory cell after writing reference data therein, are supplied to the second sense amplifier, which compares the first and second signals to output a comparison result representative of the data stored in the memory cell. During a test operation, a third signal based on the first output and a fourth signal based on an output from a voltage supply circuit are supplied to the second sense amplifier, which outputs a comparison result of the third and fourth signals as a test result.

Abstract: A data reading method is provided. The method includes: selecting a target physical page of a target wordline of a rewritable non-volatile memory module; identifying a plurality of distinguishing code patterns corresponding to the target physical page and corresponding one or more transition read voltages; using the one or more transition read voltages to read the target physical page to obtain a distinguishing code of each of a plurality of target memory cells of the target physical page; using one or more assisting read voltage sets corresponding to the one or more transition read voltages to read the target page to obtain an assisting bit value of each of the target memory cells of the target physical page; and combining the distinguishing code and the assisting bit value of each of the target memory cells to obtain an enhanced read bit value of each of the target memory cells.

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

Abstract: A method and system for estimating a state of health using battery model parameters are provided. The system includes a battery model parameter extractor that is configured to extract liquid-phase diffusivity of Li-ion parameters and a storage unit that is configured to store a mapping table in which states of health (SOH) for each liquid-phase diffusivity of Li-ion parameter are mapped. In addition, a SOH estimator is configured to use the mapping table to estimate the SOH that corresponds to a liquid-phase diffusivity of Li-ion extracted from the battery model parameter extractor.

Abstract: Nonvolatile memory devices and methods of fabricating the nonvolatile memory devices are provided. The nonvolatile memory devices may include a stacked structure including a plurality of conductive films and a plurality of interlayer insulating films stacked in an alternate sequence on a substrate and a vertical channel structure extending through the stacked structure. The plurality of conductive films may include a selection line that is closest to the substrate among the plurality of conductive films. The selection line may include a lower portion and an upper portion sequentially stacked on the substrate, and a side of the upper portion of the selection line and a side of the lower portion of the selection line may have different profiles.

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with an array of bitcells accessible via wordlines arranged in rows and bitlines arranged in columns. The integrated circuit may include source lines coupled to the bitcells. The integrated circuit may include source line drivers coupled between the wordlines and the source lines, and the source line drivers may allow the source lines to be used as switched source lines.