Abstract: A transistor includes a channel layer including an oxynitride semiconductor doped with at least one of hafnium (Hf) and zirconium (Zr), a source on one side portion of the channel layer and a drain on another side portion of the channel layer, a gate corresponding to the channel layer, and a gate insulation layer between the channel layer and the gate.

Abstract: A method of transferring a layer including: a) providing a layer joined to an initial substrate with a binding energy E0; b) bonding a front face of the layer on an intermediate substrate according to an intermediate bonding energy Ei; c) detaching the initial substrate from the layer; e) bonding a rear face onto a final substrate according to a final bonding energy Ef; and f) debonding the intermediate substrate from the layer to transfer the layer onto the final substrate; step b) comprising a step of forming siloxane bonds Si—O—Si, step c) being carried out in a first anhydrous atmosphere and step f) being carried out in a second wet atmosphere such that the intermediate bonding energy Ei takes a first value Ei1 in step c) and a second value Ei2 in step f), with Ei1>E0 and Ei2<Ef.

Abstract: A method of manufacturing a liquid discharge head is provided. The method includes forming a heating element on a substrate in which a semiconductor element is arranged. The method further includes forming a protection layer to contact an upper surface of the heating element. Annealing is performed in a hydrogen-containing atmosphere before the step of forming the protection layer.

Abstract: A semiconductor light emitting device includes a light emitting structure, a first electrode unit, and a second electrode unit. The light emitting structure includes a first and second conductivity-type semiconductor layer, an active layer. The first electrode unit includes a first electrode pad and a first electrode finger extending from the first electrode pad, and having an annular shape with an open portion. The second electrode unit includes a second electrode pad and a second electrode finger extending from the second electrode pad, and has an annular shape with an open portion. One of the first and second electrode units substantially surrounds the other, and the center of the annular shape of at least one of the first and second electrode units is spaced apart from the center of the upper surface of the light emitting structure.

Abstract: A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film.

Abstract: The resistivity of a silicon boule may vary along its length, thereby making a uniform ion implantation process sub-optimal. A system and method for measuring a resistivity of a substrate, and processing the substrate based on that measured resistivity is disclosed. The system includes a resistivity measurement system, a controller and an ion implanting system, where the controller configures the ion implantation process based on the measured resistivity of the substrate.

Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.

Abstract: An integrated circuit with a power layout includes at least one power grid cell. Each power grid cell includes a first power layer configured to be electrically coupled to a first power supply voltage, and a second power layer separate from the first power layer and configured to be electrically coupled to a second power supply voltage different from the first power supply voltage. The first power layer has conductive lines configured to surround a conductive element electrically connected to the second power layer.

Abstract: A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric cap in the cap opening and on the metal line; forming an interconnect dielectric layer over the dielectric cap and the second dielectric layer; forming an interconnect opening in the interconnect dielectric layer; removing a portion of the dielectric cap exposed by the interconnect opening selective to the interconnect dielectric layer, the second dielectric layer, and the metal line; and forming an interconnect structure in the interconnect opening, the interconnect structure comprising a contact line above a via, the via having an upper via portion with angled sidewalls and a lower via portion with substantially vertical sidewalls.

Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.

Abstract: A laser annealing method for executing laser annealing by irradiating a semiconductor film formed on a surface of a substrate with a laser beam, the method including the steps of, generating a linearly polarized rectangular laser beam whose cross section perpendicular to an advancing direction is a rectangle with an electric field directed toward a long-side direction of the rectangle or an elliptically polarized rectangular laser beam having a major axis directed toward a long-side direction, causing the rectangular laser beam to be introduced to the surface of the substrate, and setting a wavelength of the rectangular laser beam to a length which is about a desired size of a crystal grain in a standing wave direction.

Abstract: A semiconductor device includes a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode being adjacent to the body region. The body region, the drift zone, the source region and the drain region are disposed in a first semiconductor layer having a first main surface. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The transistor further includes a drift control region arranged adjacent to the drift zone, the drift control region being disposed over the first main surface.

Abstract: A semiconductor device includes a substrate and a via extending through the substrate. A first insulating layer is disposed on sidewalls of the via. An electrically conductive material is disposed in the via over the first insulating layer to form a TSV. A first interconnect structure is disposed over a first side of the substrate. A semiconductor die or a component is mounted to the first interconnect structure. An encapsulant is disposed over the first interconnect structure and semiconductor die or component. A second interconnect structure is disposed over the second side of the substrate. The second interconnect structure is electrically connected to the TSV. The second interconnect structure includes a second insulating layer disposed over the second surface of the substrate and TSV, and a first conductive layer disposed over the TSV and in contact with the TSV through the second insulating layer.

Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.

Abstract: A method for preparing graphene by reaction with Cl2 based on annealing with assistant metal film is provided, comprising the following steps: applying normal wash to a Si-substrate, then putting the Si-substrate into a reaction chamber of a CVD system and evacuating, rising the temperature to 950° C.-1150° C. gradually, supplying C3H8 and carbonizing the Si-substrate for 3-10 min; rising the temperature to 1150° C.-1350° C. rapidly, supplying C3H8 and SiH4, growing a 3C—SiC hetero-epitaxial film on the carbonized layer, and then reducing the temperature to ambient temperature under the protection of H2 gradually, introducing the grown sample wafer of 3C—SiC into a quartz tube, heating to 700-1100° C., supplying mixed gas of Ar and Cl2, and reacting Cl2 with 3C—SiC to generate a carbon film, applying the sample wafer of carbon film on a metal film, annealing at 900° C.-1100° C.

Abstract: An evaporation apparatus comprises a chamber configured to contain at least one dispensing nozzle and at least one substrate to be coated. The chamber has at least one adjustable shielding member defining an adjustable aperture. The member is positioned between the at least one dispensing nozzle and the at least one substrate. The aperture is adjustable in at least one of the group consisting of area and shape. The at least one adjustable shielding member has a heater.

Abstract: A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract: An SiC single crystal includes a low dislocation density region (A) where the density of dislocations each of which has a Burgers vector in a {0001} in-plane direction (mainly a direction parallel to a <11-20> direction) is not more than 3,700 cm/cm3. Such an SiC single crystal is obtained by: cutting out a c-plane growth seed crystal of a high offset angle from an a-plane grown crystal; applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range; cutting out a c-plane growth crystal of a low offset angle from the obtained c-plane grown crystal; and applying c-plane growth so that the density of screw dislocations introduced into a c-plane facet may fall in a prescribed range. An SiC wafer and a semiconductor device are obtained from such an SiC single crystal.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The single crystal silicon substrate is exposed to an anisotropic etchant that undercuts the single crystal silicon. By controlling the length of the etch, single crystal silicon islands or smooth vertical walls in the single crystal silicon may be created.

Abstract: A flat panel detector includes a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element includes: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor includes a first electrode and a second electrode. The first electrode includes an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.