Abstract: A method of fabricating an integrated circuit (IC) is disclosed. The method includes providing a substrate having a conductive feature. A dielectric layer is formed over the substrate, having an opening to expose the conductive feature. A tungsten (W) capping layer is formed over the conductive feature in the opening without using fluorine-containing gases. A bulk W layer is formed over the W capping layer.

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, third, fourth, fifth, sixth, and seventh semiconductor regions. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first electrode and the first semiconductor region. The third and fourth semiconductor regions are provided between the first electrode and the second semiconductor region. The fifth semiconductor region is positioned between the third semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The sixth semiconductor region is positioned between the fourth semiconductor region and the second electrode, and is provided between the first semiconductor region and the second electrode. The seventh semiconductor region is provided between the fifth semiconductor region and the second electrode.

Abstract: Described herein is a method and precursor composition for depositing a multicomponent film. In one embodiment, the method and composition described herein is used to deposit a germanium-containing film such as Germanium Tellurium, Antimony Germanium, and Germanium Antimony Tellurium (GST) films via an atomic layer deposition (ALD) and/or other germanium, tellurium and selenium based metal compounds for phase change memory and photovoltaic devices. In this or other embodiments, the Ge precursor used comprises trichlorogermane.

Abstract: Ink compositions comprising polythiophenes and aprotic organic solvents that are formulated for inkjet printing the hole injecting layer (HIL) of an organic light emitting diode (OLED) are provided. Also provided are methods of inkjet printing the HILs using the ink compositions.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract: A method for treating at least one first material layer including siloxane bonds, wherein at least one surface can be interlocked with a surface of a second material layer by direct bonding, the method including: at least one forced diffusion at a temperature greater than or equal to 30° C., at least in the first material layer, of chemical species including at least one pair of free electrons and at least one labile proton; and converting at least one portion of the siloxane bonds into silanol bonds in at least one portion of the first material layer extending from the surface to a depth greater than or equal to approximately 10 nm.

Abstract: A strained silicon material layer is bonded to a relaxed silicon material layer. The strained silicon material and any defect containing region formed during bonding are completely removed from a second device region, while a portion of the strained silicon material layer remains in a first device region. A relaxed silicon material portion is epitaxially formed on an exposed portion of the relaxed silicon material layer. A high performance nFET device, in which leakage is not a main concern, can be formed on the remaining portion of the strained silicon material layer in the first device region, and a pFET device or a low leakage nFET device can be formed on the epitaxially formed relaxed silicon material portion.

Abstract: A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package is disclosed. The method comprises preparing a wafer for bonding to a semiconductor package. The wafer comprises a low resistance substrate containing a RDL and a TSV for making an input/output (I/O) connection point of the semiconductor package available at another location. The RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation trench. The TSV is bounded by the isolation trench and the RDL. Preparing the wafer for bonding may comprise preparing the isolation trench that bounds the conduction path for the RDL through the low resistance substrate and bounds a vertical conduction path in a pillar for the TSV in the low resistance substrate, filling the isolation trench with isolation trench material, and preparing a wafer bonding surface.

Abstract: Provided is a method for manufacturing a p-type MOSFET, including: forming a part of the MOSFET on a semiconductor substrate including source/drain regions, a replacement gate, and a gate spacer; removing the replacement gate stack of the MOSFET to form a gate opening; forming an interface oxide layer on the exposed surface of the semiconductor substrate; forming a high-K gate dielectric layer on the interface oxide layer; forming a first metal gate layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer.

Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first area and a second area. A first metal layer structure is formed which includes at least a first metal portion in the first area and a second metal portion in the second area. A plating mask is formed on the first metal layer structure to cover the second metal portion, and a second metal layer structure is plated on and in ohmic contact with the first metal portion of the first metal layer structure.

Abstract: A method of manufacturing an organic light emitting structure is provided as follows. A first electrode is formed on a lower substrate. A pixel defining layer is formed adjacent to the first electrode on the lower substrate. A preliminary charge transport layer is formed on the first electrode and the pixel defining layer. An organic light emitting layer is formed on the preliminary charge transport layer. The preliminary charge transport layer is selectively etched to form a charge transport layer. A second electrode is formed on the organic light emitting layer.

Abstract: A semiconductor package without a chip carrier formed thereon and a fabrication method thereof. A metallic carrier is half-etched to form a plurality of grooves and metal studs corresponding to the grooves. The grooves are filled with a first encapsulant and a plurality of bonding pads are formed on the metal studs. The first encapsulant is bonded with the metal studs directly. Each of the bonding pads and one of the metal studs corresponding to the bonding pad form a T-shaped structure. Therefore, bonding force between the metal studs and the first encapsulant is enhanced such that delamination is avoided. Die mounting, wire-bonding and molding processes are performed subsequently. Since the half-etched grooves are filled with the first encapsulant, the drawback of having pliable metallic carrier that makes transportation difficult to carry out as encountered in prior techniques is overcome, and the manufacturing cost is educed by not requiring the use of costly metals as an etching resist layer.

Abstract: The purpose is to provide a phosphor particle dispersion liquid in which the phosphor particles do not settle out when the phosphor dispersion liquid is left to stand. The phosphor dispersion liquid contains phosphor particles, clay mineral particles, inorganic particles, and a solvent. The phosphor dispersion liquid has viscosity ?1 of 10 to 500 mPa·s at a shear rate of 1000 (1/s) at 25° C., and viscosity ?2 of 1.0×103 to 1.0×105 mPa·s at a shear rate of 1 (1/s) at 25° C.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The method includes following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region.

Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.

Abstract: A semiconductor device fabrication method includes forming a barrier layer upon a dielectric layer, forming a pillar interconnect structure upon the barrier layer, forming solder upon the pillar interconnect structure, reflowing the solder to release solder voids, forming a perimeter material around at least a portion of an exposed sidewall of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming the solder upon the pillar interconnect structure, forming a perimeter material on exposed surfaces of the pillar interconnect structure, and removing the barrier layer on the surface of the dielectric layer exterior to the pillar interconnect structure.

Abstract: According to an exemplary embodiment, a method of forming a Micro Electro Mechanical System (MEMS) device is provided. The method includes the following operations: providing a substrate; forming a catalyst layer over the substrate; patterning the catalyst layer; forming a carbon nanotube based on the catalyst layer; forming a getter layer over the carbon nanotube and the substrate; and etching back the getter layer to expose the carbon nanotube. According to an exemplary embodiment, a method of forming a MEMS device is provided. The method includes the following operations: providing a substrate; forming a catalyst island over the substrate; heating the substrate and the catalyst island; contacting the catalyst island with a carbon-containing gas to form a carbon nanotube; forming a getter layer over the carbon nanotube and the substrate; and etching back the getter layer to expose the carbon nanotube.

Abstract: A method of defining poly-silicon growth direction includes Step 1, forming a buffer layer on a substrate; Step 2, forming a regular graphene array; Step 3, forming an amorphous silicon thin film on the buffer layer, which the regular graphene array has formed thereon; and Step 4, transferring the amorphous silicon thin film into poly-silicon with an excimer laser anneal process. The growth direction of the poly-silicon as being formed can be controlled according to the present method of defining poly-silicon growth direction. Accordingly, the grain size of the poly-silicon can be raised.

Abstract: According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film.

Abstract: An image sensor includes a photoelectric conversion region formed in a substrate, an interlayer insulation layer formed over a front side of the substrate, a carbon-containing layer doped with impurities and formed over a back side of the substrate, and a color filter and a micro-lens formed over the carbon-containing layer.