Abstract: A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.

Abstract: The invention pertains to an output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise. The circuit includes an MOS inverter circuit having a first node adapted to be connected to one terminal of a power supply and a second node adapted to be connected to the other node, and having an input for receiving an input signal and an output for providing an output signal adapted to be connected to an output transistor. The circuit also has a first MOS transistor of one polarity type and one mode having its source-drain circuit coupled in series with the first node of the inverter circuit, and a second MOS transistor opposite in either polarity type or mode from the first MOS transistor, having its source-drain circuit coupled in series with the other node of the inverter circuit.

Abstract: A circuit is provided which modifies a digital drive signal to produce a time variant drive signal for application to a gate of a bus driver transistor. The circuit's purpose is to reduce the amplitude of ringing on a bus, due to rapid discharging of current from the bus, in order to prevent unintentional triggering of devices connected to the bus. A P-channel MOS transistor and N-channel MOS transistor are connected so that the digital drive signal is simultaneously applied to the source of the P-channel MOS transistor and to the drain of the N-channel MOS transistor. The gate of the driver transistor is connected to the drain of the P-channel MOS transistor and the source of the N-channel transistor.

Abstract: An ECL logic gate includes an input stage, an output stage, and a multifunction current mirror circuit. The input stage includes a plurality of input transistors, a reference transistor, and an output which indicates the relative conductivities of said reference transistor as compared to one or more of the input transistors. This output is coupled to the output stage. A current mirror circuit having first and second current paths is provided in which the input stage is coupled in series with the first current path, and the output stage is coupled in series with the second current path.

Abstract: A circuit for use in conjunction with an enable/disable gate of a three state logic circuit for disabling the outputs of the logic circuit during power up of the voltage supply to maintain a high impedance output state at the outputs of the logic circuits. The circuit includes a voltage level detector stage comprising a switching transistor that is held in a non-conducting state until the voltage supply reaches a predetermined potential after which the transistor is turned on and a pair of transistors configured as a current mirror with their bases coupled to the output of the switching transistor. The pair of transistors are turned on until the switching transistor is turned on to provide sufficient base current drive to a disable transistor of the enable/disable gate such that the logic circuit is disabled accordingly. An aspect of the invention is that the power up circuit draws little additional power during normal operation of the logic circuit.

Abstract: A configurable logic array comprises a plurality of configurable logic elements variably interconnected in response to control signals to perform a selected logic function. Each configurable logic element in the array is in itself capable of performing any one of a plurality of logic functions depending upon the control information placed in the configurable logic element. Each configurable logic element can have its function varied even after it is installed in a system by changing the control information placed in that element. Structure is provided for storing control information and providing access to the stored control information to allow each configurable logic element to be properly configured prior to the initiation of operation of the system of which the array is a part. Novel interconnection structures are provided to facilitate the configuring of each logic element.

Abstract: A circuit which provides additional drive current during substantially the entire transition of an output signal from a logical one to a logical zero state, thereby causing the pulldown transistor in the TTL output stage to rapidly turn on, providing increased switching speed between logical one and logical zero output state for a given power consumption. Alternatively, for a given switching speed, power consumption is reduced.

Abstract: The invention provides a circuit for use with a standard bidirectional databus having an active current device providing a first logic level in combination with a selectably jumpered passive resistance device providing a second logic level, the active element responsive to an enable signal whereby tristating the bus write drivers and reading the bus will sense a configuration determined by selection of the jumper.

Abstract: A voltage variable FET resistor includes a FET network comprising a plurality of FET segments each of which have a predetermined gate width and a voltage divider network including a plurality of fixed resistors coupled to the gates of the plurality of FET segments for providing a different gate width of each of the FET segments and the resistance of each of the fixed resistors is chosen to provide a predetermined relationship between the control voltage and the channel resistance of the voltage variable FET resistor.

Abstract: A sense amplifier of the invention includes a PMOS transistor, the source and the drain of which are respectively connected to a power source and an EP-ROM as a signal source to be detected, and the gate and the drain of which are controlled to be at the same potential, a PMOS transistor connected to the power source and the EP-ROM in parallel with the PMOS transistor, and a ratio circuit in which the gate of one PMOS transistor and an NMOS transistor constituting a CMOS transistor is connected to the signal source. This arrangement of the invention enables a high speed operation.

Abstract: This is a superconducting digital logic amplifier for interfacing superconductor circuits with semiconductor circuits. It provides a gigahertz amplifier to convert low voltage superconducting logic signals to higher voltage signals, suitable for semiconductor signal processing circuits. It may, for example, provide a factor of ten voltage gain to raise the 2.5 mV Josephson logic signals of conventional metallic superconductor circuitry to 25 mV signals for input into inexpensive semiconductor amplifiers which, in turn, can power semiconductor logic circuitry. Generally, it utilizes a first series string of Josephson junctions in series with an input Josephson junction to provide a series combination which is then connected in parallel with a second string of higher critical current Josephson junctions. The input signal is introduced between the first series string and the input Josephson junction, and the output terminal is connected at the common connection opposite the input Josephson junction.

Abstract: In accordance with the teachings of this invention, a novel PLA row driver circuit is provided which utilizes a minimum number of components, thereby minimizing integrated circuit surface area, and thus reducing cost, and minimizing stray capacitance, thereby increasing speed of operation. Furthermore, in accordance with the teachings of this invention, a circuit is provided which, while utilizing a minimum number of components, provides a first VOL level to the row line during normal operation of the device, and a second, higher VOL level to the row line during programming.

Abstract: A plurality of RAM chips, a V.sub.CC power supply terminal and a V.sub.SS power supply terminal are all formed on one wafer. Each of the RAM chips comprises an MOS circuit comprising a V.sub.CC power supply line and a V.sub.SS power supply line, a power supply terminal and a ground terminal. The ground terminal is connected to the V.sub.SS power supply line through an N channel MOS transistor, and the power supply terminal is connected to the V.sub.CC power supply line. The MOS transistor has a gate connected to a power supply terminal through a fuse element. The power supply terminals and the ground terminals in the plurality of RAM chips are connected to the V.sub.CC power supply terminal and the V.sub.SS power supply terminal, respectively, by aluminum interconnections. When a power-supply voltage is applied between the V.sub.CC power supply terminal and the V.sub.

Abstract: A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines.

Abstract: When a counter-part power supply designator of a first LSI designates that the counter-part power supply voltage of another LSI is a first power supply difference which is the same as the power supply difference of its own, an output circuit control controls an output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the first power supply voltage. When the counter-part power supply voltage designator designates that the counter-part power supply voltage difference, lower than the first power supply voltage difference, the output circuit control controls the output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the second power supply voltage difference. Thus, a plurality of LSIs can be operated at mutually different power supply voltages.

Abstract: A single plane dynamic decoder wherein a typical decoder row comprises a P-channel transistor connected between a positive supply and a first node, a second N-channel transistor connected between ground potential and a second node, and a plurality of series-connected devices connected between the first node and the second node. The gates of the intermediate N-channel devices are connected to a corresponding input signal such that the intermediate devices are enabled or disabled depending on the state of the associated input. The gate of the P-channel device is connected to a clock signal such that it is enabled by a first clock phase and disabled by a second clock phase. The N-channel device is connected to the clock signal such that it is enabled by the second clock phase and disabled by the first clock phase. Thus, the first node is precharged when the P-channel device is enabled. This precharge activity occurs serially and hierarchically down the row depending on the state of the respective input signals.

Abstract: The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock is used to provide an initiation signal which starts the propagation of input data through the array. A means is coupled to the clock for sending a dummy data pulse through the second data path upon receipt of the initiation signal, and a detecting means detects the completion of the passage of the dummy data through the second path and supplies a completion signal in response.

Abstract: A threshold comparator having hysteresis wherein the repeatable threshold levels are established by multiple current paths and resistance ratios, which provides an under-voltage lock-out signal. The current paths are established by transistors fabricated on a common substrate and include a split collector P-N-P transistor that provides the distribution of the input signal to the various current paths. The turn-on and turn-off threshold points of the circuit according to the present invention are established by resistance ratios which are more easily maintained than are absolute resistance values. Similarly, when implemented on a common substrate, the remaining component values may be selected so that the thresholds values are nearly independent of temperature, providing an easily manufactured, high yield circuit.

Abstract: The invention relates to an output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply. The output circuit of the invention includes two terminals adapted to be connected to a power supply capable of providing a supply voltage. The output circuit includes an MOS transistor having a substrate, source and drain terminals and a gate, one of the source and drain terminals being coupled to one of the power supply terminals. A second transistor has three terminals including a control terminal and two other terminals, one of which is coupled to the other of the source and drain terminals of the MOS transistor, and the other of which is coupled to the other power supply terminal. An output terminal is coupled between the one terminal of the second transistor and the other of the source and drain terminals of the MOS transistor.

Abstract: There is disclosed herein a bimorph using ultraviolet setting glue to laminate the structure and having etched back metalization patterns on the surfaces of the piezoelectric film used to make the bimorph to minimize the possibility of shorting and to eliminate electrostatic pinning and to increase the mechanical reliability and lifetimes of the electrical contacts. Also disclosed is a method for making the bimorph and a method for registering the bimorph on a light modulator. There is also disclosed a bimorph light modulator consisting of a substrate on which there is attached an fiber optic input light guide and a fiber optic output light guide. There is a gap between these light guides through which light passes as it is coupled between said light guides. A bimorph is affixed to the substrate with a shutter attached to one end of the bimorph such that the shutter is registered in the gap so as to block light coupling when the bimorph is in the unenergized state.