Abstract: A reprogrammable logic array is characterized by the use of a RAM fuse to selectively control the transfer of variable from input lines to intersecting output combination lines of the array. The configuration of the combiner array is programmed by writing to all of the RAM locations that are associated with the array. If a connection is to be made, a logical "1" is written to the RAM cell for that connection and if no connection is desired, a "0" is written to the RAM cell. The array which includes a novel input interface, can be quickly and easily reprogrammed simply by writing to the appropriate RAM cells. The RAM fuses may function as standard static RAM if the device does not need to function as a combiner.

Abstract: An accelerated switching input circuit includes an emitter coupled logic stage having two transistors. The first transistor receives at its base an input signal and the second transistor receives at its base a control signal generated from the signal at the collector of the first transistor. A third transistor (T.sub.6) has its base connected to the collector of the first transistor (T.sub.3). A first resistor (R.sub.10), a second resistor (R.sub.11) and a third resistor (R.sub.12) are disposed in series between the emitter of the third transistor and a reference voltage (U.sub.REF) source. The point B common to the resistors R.sub.11 and R.sub.12 is coupled to the base of the second transistor (T.sub.4).

Abstract: A flip-flop includes two gates each having a CMOS circuit and a bipolar circuit. One bipolar circuit related to one of the gates includes first and second bipolar transistors, and the other bipolar circuit includes third and fourth bipolar transistors. A discharge circuit discharges the base of the first bipolar transistor in response to a change in a second input and discharges the base of the third bipolar transistor in response to a first input. The first and second inputs are complementary inputs. A charge cirucit charges the base of the second bipolar transistor in response to the second input and charges the base of the fourth bipolar transistor in response to the first input.

Abstract: A TTL-level-output interface circuit includes a biCMOS inverter coupled between a voltage supply terminal and a ground terminal; a first npn transistor coupled between the voltage supply terminal and a TTL interface terminal and a second npn transistor connected in series with the first npn transistor between the TTL interface terminal and the ground terminal; an n.phi. network coupled between the TTL output terminal and the base of the second npn transistor by an n-channel MOSFET, which has its gate connected to the inverter input terminal. When a high input signal is applied to the inverter input terminal, the n-channel MOSFET couples the n.phi. network to the base of the second npn transistor, in order both to limit the base current of the second npn transistor in order to prevent saturation of the second npn transistor, and to enable current to be conducted to the base of the second npn transistor 56 through the n.phi.

Abstract: In one embodiment, a semiconductor device which generates a substantially constant reference voltage over a broad temperature range upon application of a power supply voltage thereto, wherein a current substantially inversely proportional to the value of a load resistor is drawn through the resistor to generate a substantially constant voltage across the resistor. The current through the resistor is the sum of a first current and a second current. The first current is determined by the absolute value of the threshold voltage of a depletion mode FET (DFET) in conjunction with an associated first resistor. The second current is determined by the threshold voltage of an enhancement mode FET (EFET) in conjunction with an associated second resistor. As the temperature of the device changes the first and second currents will change in opposite directions with the sum being changed inversely proportional to the change in resistance with temperature of the load resistor.

Abstract: An emitter-coupled logic circuit, including first to fourth n-p-n transistors, the first transistor having its base connected to a first input signal source and its collector connected to a first supply voltage source, the second transistor having its base connected to a second input signal source and its collector connected to the first supply voltage source, the first and second transistors having their emitters connected to a second supply voltage source via a constant current source, an n-p-n transistor type emitter-follower circuit having an input terminal connected to the collector of the first transistor and its collector connected to the first supply voltage source, a load element connected between the first supply voltage source and the collector of the first or second transistor, the third transistor having its base connected to a reference voltage source and its collector connected to the first supply voltage source, the fourth transistor having its base connected to the base of the first transisto

Abstract: An inverter portion, which is to be basic logic circuit, includes switching FETs corresponding to input terminals and a load FET. A logic signal inputted into each of the input terminals drives each corresponding switching FET, thereby to output a prescribed logic signal from an output terminal. Further, a load for restricting a current flowing in the load FET is connected between the gate and the source of the load FET. In addition, a load current control FET is provided for controlling the current in this load. A gate potential of the load current control FET is produced by a diode OR circuit. The diode OR circuit outputs a logic OR of the logic signals inputted into the respective input terminals, and supplies it to the gate of the load current control FET as a load current control signal.

Abstract: The described embodiment of the present invention includes a combinatorial circuit, such as a multiplexor. All or a portion of the input signals to the multiplexor are also provided to a transition detector. Upon detecting a transition, the transition detector provides a signal which temporarily suppresses the operation of the combinatorial circuit prior to a portion of the combinatorial circuit which is sensitive to glitches and/or timing errors. The delay allows time for glitches and/or timing errors to dissipate. This provides a cleaner signal for the sensitive portion to avoid the errors that the suppressed glitches and/or timing errors may cause.

Abstract: A CMOS push-pull output buffer is powered by a low-voltage (e.g., +3.3 V) supply, but is able to withstand elevation of its output node to higher voltage without sinking large currents into the low-voltage supply. Thus, this buffer is able to operate tied to a bus that has various higher-voltage sources also operating on the bus. The P-channel pull-up transistor of this buffer has another P-channel transistor connecting its gate to the output node so that this gate will follow the voltage of the output node and thus keep the pull-up transistor from conducting from the output node to the power supply. The inverter which drives this gate of the P-channel pull-up transistor is also protected from reverse current into its low-voltage power supply by a series N-channel transistor which will exhibit body effect and is sized to present a significant resistance.

Abstract: Digital logic circuitry designed to operate on a low voltage power supply without substantial transistor saturation thereby achieving lower power and higher opeational speeds. A non-saturating inverter with a low voltage swing can be made with one transistor using standard bipolar production processes and without clamp diodes. The novel circuitry uses logic units which can be modularly combined to form various other logical functions such as inverters, gates, flip-flops, etc. The preferred logic units use a transistor with the base connected by a load resistor to a first current network. The logical input is between the load resistor and base. The emitter is connected either directly or via one or more resistors to a second current network. The first and second power networks are constructed and arranged to provide a voltage-varying profile across both networks which are preferably complementary to provide nearly constant differential voltages across the logic units.

Abstract: An electronic circuit is disclosed having a sample/hold amplifier connected to an adaptive amplifier. A plurality of such electronic circuits may be configured in an array of rows and columns. An input voltage vector may be compared with an analog voltage vector stored in a row or column of the array and the stored vector closest to the applied input vector may be identified and further processed. The stored analog value may be read out of the synapse by applying a voltage to a read line. An array of the readable synapses may be provided and used in conjunction with a dummy synapse to compensate for an error offset introduced by the operating characteristics of the synapses.

Abstract: A current-voltage converting circuit applicable to a linear integrated circuit of CMOS-type having a wide-ranged operational voltage, comprising a buffer circuit for buffering and amplifying a current being input to an input terminal; a gain circuit for outputting a voltage in proportion to the output voltage of the buffer circuit; and a current reference circuit constituted in a current mirror by P-channel transistors; N-channel transistors and a reference voltage and is adapted to supply a constant voltage to gates of P-channel transistors provided in the gain circuit.

Abstract: The present invention is a neural network circuit including a plurality of neuron circuits. Each neuron circuit has an input node for receiving an input signal, an output node for generating an output signal and a self-feedback control node for receiving a self-feedback signal. An interconnection device having an electrically controllable conductance is connected between the input nodes of each pair of neuron circuits. The neural network circuit is consequently programmable via the voltages applied to the self-feedback control nodes and the interconnection devices. Such programmability permits the neural network circuit to store certain sets of desirable steady states. In the preferred embodiment the individual neuron circuits and the interconnection devices are constructed in very large scale integration CMOS. Thus this neural network circuit can be easily constructed with large numbers of neurons.

Abstract: The physical realization of new solutions of wave propagation equations, such as Maxwell's equations and the scaler wave equation, produces localized pulses of wave energy such as electromagnetic or acoustic energy which propagate over long distances without divergence. The pulses are produced by driving each element of an array of radiating sources with a particular drive function so that the resultant localized packet of energy closely approximates the exact solutions and behaves the same.

Abstract: A merged enhancement/depletion-mode FET circuit and a complementary FET logic circuit have enhanced operation speed and reduced power dissipation. Serially connected depletion mode and enhancement mode transistors function as an output stage for the complementary FET logic stage, with the gate of an n-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage and the output of an n-channel depletion-mode transistor being connected to the common terminal or output terminal of the output stage. In an alternative embodiment, a p-channel enhancement-mode transistor is connected in parallel with the n-channel depletion-mode transistor with the gate of the p-channel enhancement-mode transistor being connected to the output of the complementary FET logic stage. The circuitry is particularly useful in compound semiconductor circuits using MESFETS and heterojunction-FETs.

Abstract: A bipolar/CMOS decoder circuit for providing a decoded output signal includes a plurality of pull-up gate circuits (14a) and a pull-down circuit (16). Each of the gate circuite (14a) is formed of a pull-up P-channel MOS transistor (P1), a pull-down N-Channel MOS transistor (N1), and a pull-up bipolar transistor (Q1). The pull-down circuit (16) is formed of a single pull-down current source, N-channel MOS transistor (N.0.). The bipolar transistors and CMOS transistors are merged in a common semiconductor substrate in order to form the decoder circuit which has a high noise margin and low pattern sensitivity even with a large number of inputs.

Abstract: A semiconductor integrated circuit having a signal level converter is disclosed. The converter includes a plurality of first insulated gate field effect transistors each having a thin gate insulating film and formed on a low voltage or a ground voltage line side and a plurality of second insulated gate field effect transistors each having a thick gate insulating film and formed on a high voltage power supply line side.

Abstract: Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.

Abstract: A semiconductor device used for, particularly, an output stage of a logic circuit is formed by a Schottky.barrier.diode clamping transistor. A clamping circuit is provided between a collector and a base for clamping a collector potential. The clamping circuit is formed by a Schottky.barrier.diode (SBD) and a series connected resistance coupled to the Schottky.barrier.diode. A collector resistance is divided by resistance division using the series resistance (FIG. 6).

Abstract: A multiplexer circuit is disclosed, for use with such signal sources as focal plane detector arrays, which contains a large number of parallel branches, each of which includes a transconductance MOSFET amplifier and a MOSFET switch of opposite channel polarity from the amplifier. The amplifier in each branch receives high impedance voltage signals orginating from its individual detector and converts them with high power gain into current signals which feed into the common output line whenever the switch in the same branch is turned on. The multiplexer branches, together with the multiplexer control logic, and other electronic devices, are all included on a signal IC chip which provides CMOS logic.