Patents Examined by David S. Blum
  • Patent number: 10930570
    Abstract: Methods for manufacturing a display device are provided. A representative method includes: providing a substrate having a plurality of sub-pixel locations; providing a carrier substrate supporting a plurality of light emitting diodes (LEDs); conducting a testing to at least one of the plurality of LEDs on the carrier substrate; transferring at least a portion of the plurality of LEDs from the carrier substrate to the substrate; fixing the portion of the plurality of LEDs to the substrate; providing an insulator over the substrate; and providing a first electrode electrically connected to at least one of the portion of the plurality of LEDs.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 23, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Hsiung Chang, Ting-Kai Hung, Hsiao-Lang Lin
  • Patent number: 10886172
    Abstract: Methods of wordline separation in semiconductor devices (e.g., 3D-NAND) are described. A metal film is deposited in the wordlines and on the surface of a stack of spaced oxide layers. The metal film is removed by high temperature oxidation and etching of the oxide or low temperature atomic layer etching by oxidizing the surface and etching the oxide in a monolayer fashion. After removal of the metal overburden, the wordlines are filled with the metal film.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: January 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Yihong Chen, Ziqing Duan, Abhijit Basu Mallick, Kelvin Chan
  • Patent number: 10873029
    Abstract: A vapor deposition mask preparation body in which a metal mask is provided on one surface of a resin plate for obtaining a resin mask, and a protective sheet with peel strength not less than about 0.0004 N/10 mm and less than about 0.2 N/10 mm in conformity with JIS Z-0237:2009 is provided on the other surface of the resin plate is prepared, with respect to the vapor deposition mask preparation body, the resin plate is irradiated with laser light from the metal mask side to form a resin mask opening corresponding to a pattern to be produced by vapor deposition in the resin plate, and the protective sheet is peeled off from the resin mask in which the resin mask opening corresponding to the pattern to be produced by vapor deposition is formed.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 22, 2020
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Kumiko Hokari, Yasuko Sone, Katsunari Obata
  • Patent number: 10854641
    Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: December 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Atsushi Umezaki, Shunpei Yamazaki
  • Patent number: 10847554
    Abstract: A method for fabricating an array substrate motherboard, an array substrate motherboard and a detection method are provided. The method for fabricating an array substrate motherboard includes depositing a first film on a substrate, wherein a first gap is present between the edge of the first film and the edge of the substrate, coating photoresist on the substrate on which the first film is deposited, and exposing and developing the photoresist to form a first scale pattern from the photoresist. One end of the first scale pattern is flush with the edge of the substrate and the other end covers the first film.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 24, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Fangbin Fu, Huibin Guo, Shoukun Wang, Hao Han, Yongzhi Song
  • Patent number: 10840410
    Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Martin F. Schubert
  • Patent number: 10840291
    Abstract: Some embodiments provide a color image sensor and color image sampling method that uses multiple-layer pixels and is capable of producing color images without using absorption color filters (e.g., such as employed in conventional CFAs). In accordance with some embodiments of the color image sensor device and color image sampling method, frequency-dependent reflectors are incorporated between the photodetection layers of multiple-layer (e.g., two layer) pixels.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: November 17, 2020
    Assignee: Trustees of Dartmouth College
    Inventors: Leo Anzagira, Eric R. Fossum
  • Patent number: 10840310
    Abstract: A display device includes a substrate having a display area and a non-display area located at an outer periphery of the display area; a transistor layer disposed on the substrate; a plurality of partition walls disposed on the transistor layer in the display area; a light emitting element disposed between the partition walls; and a spacer configured to be disposed in the non-display area of the substrate, wherein the spacer may include a spacer body disposed on the same layer as the partition walls and on at least a portion of the transistor layer.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hye Heo, Soon Jung Wang, Eun Ju Lee
  • Patent number: 10840320
    Abstract: Systems, methods, and computer-readable media for sensing ambient light with a display assembly are provided. A display assembly may include at least one light-generating component and at least one light-detecting component, each of which may be positioned underneath a single opening in an electronic device housing.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 17, 2020
    Assignee: APPLE INC.
    Inventors: Mohammad Yeke Yazdandoost, Giovanni Gozzini, Volodymyr Borshch
  • Patent number: 10833177
    Abstract: Semiconductor device and fabrication method are provided. The method includes: providing a substrate having a fin which has first fin layers and second fin layers; forming a dummy gate structure across the fin; after forming the dummy gate structure, respectively forming a first groove and a second groove in the fin on two sides of the dummy gate structure; removing a portion of the second fin layer adjacent to the first groove to form a first fin recess; removing a portion of the second fin layer adjacent to the second groove to form a second fin recess; forming a first spacer layer in the first fin recess and forming a second spacer layer in the second fin recess; after forming the first spacer layer, forming a doped drain layer in the first groove; and after forming the second spacer layer, forming a doped source layer in the second groove.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: November 10, 2020
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10825849
    Abstract: A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2. According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 3, 2020
    Assignee: Sony Corporation
    Inventors: Takayuki Ezaki, Teruo Hirayama
  • Patent number: 10818648
    Abstract: A semiconductor module includes: a semiconductor package in which a semiconductor device is incorporated; a snubber circuit having a snubber capacitor and a snubber resistor which are connected in parallel to the semiconductor device; a first light-emitting device emitting light when residual voltage between an anode and a cathode of the semiconductor device becomes equal to or higher than first voltage; and a second light-emitting device emitting light when the residual voltage becomes equal to or higher than second voltage, wherein the first and second voltages are different from each other.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 27, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kouichi Yoshimura
  • Patent number: 10811594
    Abstract: A method for fabricating an array of pillars. The method includes fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer. The method selects between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer. For electron beam patterning, an electron beam lithography hard mask is deposited onto the metal stack, and an electron beam is used to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array. For photolithography patterning, a photolithography hard mask is deposited onto the metal stack, and photolithography is used to pattern a second array of pillars into the photolithography hard mask to produce a second resulting pillar array. The first resulting pillar array is substantially the same as the second resulting pillar array.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 20, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Prachi Shrivastava, Daniel Liu, Yuan Tung Chin
  • Patent number: 10811411
    Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Bharat V. Krishnan
  • Patent number: 10797042
    Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 6, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Wenzhen Wang, Hirotaka Takeno, Atsushi Okamoto
  • Patent number: 10797197
    Abstract: A thin film, flexible optoelectronic device is described. In an aspect, a method for fabricating a single junction optoelectronic device includes forming a p-n structure on a substrate, the p-n structure including a semiconductor having a lattice constant that matches a lattice constant of substrate, the semiconductor including a dilute nitride, and the single-junction optoelectronic device including the p-n structure; and separating the single-junction optoelectronic device from the substrate. The dilute nitride includes one or more of GaInNAs, GaInNAsSb, alloys thereof, or derivatives thereof.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 6, 2020
    Assignee: ALTA DEVICES, INC.
    Inventors: Nikhil Jain, Brendan M. Kayes, Gang He
  • Patent number: 10797151
    Abstract: The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wang, Chia-Ming Tsai, Ke-Chih Liu, Chandrashekhar Prakash Savant, Tien-Wei Yu
  • Patent number: 10790185
    Abstract: Some embodiments include a method of forming an integrated assembly. A construction is formed to include a structure having an exposed surface, and to include an opening proximate the structure. An aperture extends into the opening. A first material is deposited to form a mass along the exposed surface of the structure. Particles are sputtered from the mass and across the aperture. The particles agglomerate to form a sealant material which traps a void within the opening.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Guangjun Yang
  • Patent number: 10784315
    Abstract: A display device including a first substrate, a second substrate opposing the first substrate, a display region including a plurality of light emitting elements arranged above the first substrate, a color filter layer arranged on the second substrate in the display region including a plurality of light emitting elements, the color filter layer overlapping each of the plurality of light emitting elements respectively, a coating layer arranged between the color filter layer and the second substrate, a first inorganic insulating layer arranged above the plurality of light emitting elements, a second inorganic insulating layer above the first inorganic insulating layer, a first organic insulating arranged between the first inorganic insulating layer and the second inorganic insulating layer in a periphery region surrounding the display region, and a filler material surrounding the periphery region and filling a space, wherein the coating layer does not overlap the first organic insulating layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 22, 2020
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 10784347
    Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau