Abstract: Process kits, processing chambers, and methods for processing a substrate are provided. The process kit includes an edge ring, an adjustable tuning ring, and an actuating mechanism. The edge ring has a first ring component interfaced with a second ring component that is movable relative to the first ring component forming a gap therebetween. The second ring component has an inner thickness that is less than an outer thickness, and at least a portion of an upper surface of the second ring component is inwardly angled towards the ring first component. The adjustable tuning ring has an upper surface that contacts the lower surface of the second ring component. The actuating mechanism is interfaced with the lower surface of the adjustable tuning ring and is configured to actuate the adjustable tuning ring such that the gap between the first ring component and the second ring component is varied.

Abstract: An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 ?m is 1 aA or less.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors, contacts, and a first metal layer, where a portion of the first single crystal transistors are interconnected, where the interconnected includes the first metal layer and the contacts, and where the portion of the first single crystal transistors are interconnected forms memory control circuits; a second level overlaying the first level, the second level including a plurality of second transistors; a third level overlaying the second level, the third level including a plurality of third transistors; a fourth level overlaying the third level, the fourth level including a plurality of fourth transistors; and a second metal layer overlaying the fourth level, where the plurality of second transistors are aligned to the plurality of first transistors with a less than 40 nm alignment error.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory comprises a plurality of memory stacks neighboring each other in a first direction and a second direction, the second direction intersecting the first direction, a plurality of first liner layers covering sidewalls of memory stacks that neighbor each other in the second direction, the plurality of first liner layers extending in the second direction, a plurality of first air gaps located in spaces covered by the first liner layers, and a plurality of second air gaps located between each pair of memory stacks that neighbor each other in the first direction, the plurality of second air gaps extending in the second direction.

Abstract: Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first epitaxial layer and a second epitaxial layer formed on mesas of the semiconductor layer. The thicknesses and doping concentrations of the first and second epitaxial layers and the mesa are selected to achieve charge balance in operation. In another embodiment, the semiconductor body is lightly doped and the thicknesses and doping concentrations of the first and second epitaxial layers are selected to achieve charge balance in operation.

Abstract: A method of assessing a semiconductor substrate includes a sticking step of sticking a device layer of the semiconductor substrate to a support substrate, a thinning step of thinning the semiconductor substrate from a reverse side thereof to a thickness smaller than a finished thickness after the sticking step is carried out, and an assessing step of applying light to the semiconductor substrate from the reverse side thereof and measuring scattered light from the semiconductor substrate thereby to assess a property of the semiconductor substrate.

Abstract: A multi-junction optoelectronic device and method of fabrication are disclosed. In an aspect, the method includes forming a first p-n structure on a substrate, the first p-n structure including a semiconductor having a lattice constant that matches a lattice constant of the substrate; forming one or more additional p-n structures on the first p-n structure, each of the one or more additional p-n structures including a semiconductor having a lattice constant that matches the lattice constant of the substrate, the semiconductor of a last of the one or more additional p-n structures that is formed including a dilute nitride, and the multi-junction optoelectronic device including the first p-n structure and the one or more additional p-n structures; and separating the multi-junction optoelectronic device from the substrate. In some implementations, it is possible to have the dilute nitride followed by a group IV p-n structure.

Abstract: The present disclosure provides an organic light-emitting display panel and device. The organic light-emitting display panel includes pixel units; gate lines; and data lines intersecting with and insulated from the gate lines. None of the pixel units is provided within the hollow area, and the pixel units are provided in a periphery of the hollow area. The display area includes a full display area and a half display area, and the full display area includes first to fifth display regions. The first display region, the hollow area and the second display region are sequentially arranged along a first direction. The half display area, the hollow area, and the third display region are sequentially arranged along a second direction. A number of pixel units per unit area in the full display area is greater than a number of pixel units per unit area in the half display area.

Abstract: Provided is a method of manufacturing a nanorod. The method comprising comprises the steps of: providing a growth substrate and a support substrate; epitaxially growing a nanomaterial layer onto one surface of the growth substrate; forming a sacrificial layer on one surface of the support substrate; bonding the nanomaterial layer with the sacrificial layer; separating the growth substrate from the nanomaterial layer; flattening the nanomaterial layer; forming a nanorod by etching the nanomaterial layer; and separating the nanorod by removing the sacrificial layer.

Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.

Abstract: A semiconductor stack includes a substrate made of silicon carbide, and an epi layer disposed on the substrate and made of silicon carbide. An epi principal surface, which is a principal surface opposite to the substrate, of the epi layer is a carbon surface having an off angle of 4° or smaller relative to a c-plane. In the epi principal surface, a plurality of first recessed portions having a rectangular circumferential shape in a planar view is formed. Density of a second recessed potion that is formed in the first recessed portions and is a recessed portion deeper than the first recessed portions is lower than or equal to 10 cm?2 in the epi principal surface.

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

Abstract: A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.

Abstract: A semiconductor manufacturing apparatus according to an embodiment comprises: a lid member; a support member; an oxidation resistant member; and an oxidizing system gas introducing member. The lid member is opposed to a surface of a semiconductor substrate. The support member supports the lid member. The oxidation resistant member is opposed to a back of the semiconductor substrate. The oxidizing system gas introducing member introduces an oxidizing system gas that oxidizes the back of the semiconductor substrate.

Abstract: A packaged semiconductor device includes a leadframe (LF) having a plurality of laminate-supporting pedestals. A cured first die attach (DA) material is on an outer edge of the pedestals being an ultraviolet (UV)-curing DA material having a photoinitiator or a cured B-stage DA material. A cured thermally-curing DA material is on an area of the pedestals not occupied by the UV-curing DA material. A laminate component having bond pads on a top side is mounted top side up on the plurality of pedestals.

Abstract: Methods for manufacturing a display device are provided. A representative method includes: providing a substrate having a plurality of sub-pixel locations; providing a carrier substrate supporting a plurality of light emitting diodes (LEDs); transferring the plurality of LEDs from the carrier substrate to the substrate; and fixing the plurality of LEDs with respect to the substrate. The method also may include: positioning the substrate within a chamber; and providing an insulator over the substrate.

Abstract: A light-emitting device having a curved light-emitting surface is provided. Further, a highly-reliable light-emitting device is provided. A substrate with plasticity is used. A light-emitting element is formed over the substrate in a flat state. The substrate provided with the light-emitting element is curved and put on a surface of a support having a curved surface. Then, a protective layer for protecting the light-emitting element is formed in the same state. Thus, a light-emitting device having a curved light-emitting surface, such as a lighting device or a display device can be manufactured.

Abstract: A wafer defect analysis method according to one embodiment comprises the steps of: thermally treating a wafer at different temperatures; measuring an oxygen precipitate index of the thermally treated wafer; determining a characteristic temperature at which the oxygen precipitate index is maximized; and discriminating a type of defect region of the wafer depending on the determined characteristic temperature.

Abstract: A semiconductor package including a package substrate, a semiconductor chip on a first surface of the package substrate, a connection substrate on the package substrate and spaced apart from and surrounding the semiconductor chip, the connection substrate including a plurality of conductive connection structures penetrating therethrough, a plurality of first connecting elements between the semiconductor chip and the package substrate and electrically connecting the semiconductor chip to the package substrate, a plurality of second connecting elements between the connection substrate and the package substrate and electrically connecting the connection substrate to package substrate, a mold layer encapsulating the semiconductor chip and the connection substrate, and an upper redistribution pattern on the mold layer and the semiconductor chip and electrically connected to a corresponding one of the plurality of conductive connection structures may be provided.

Abstract: According to an embodiment of a power semiconductor device, the device includes a semiconductor body coupled to a first load terminal and a second load terminal and configured to conduct a load current between the first load terminal and the second load terminal. A trench extends into the semiconductor body along an extension direction and includes an insulator. A first electrode structure included in the trench is configured to control the load current. A second electrode structure included in the trench is arranged separately and electrically insulated from the first electrode structure. The first electrode structure and the second electrode structure are spatially displaced from each other along the extension direction such that they do not have a common extension range along the extension direction. Each of the first electrode structure and the second electrode structure is made of a metal.