Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate and a cap element over the gate stack. The cap element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element over a sidewall of the cap element and a sidewall of the gate stack.

Abstract: Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate.

Abstract: A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

Abstract: A semiconductor memory device according to an embodiment comprises a plurality of control gate electrodes, a first semiconductor layer, and a gate insulating layer. The plurality of control gate electrodes are arranged in a first direction that intersects a surface of a substrate. The first semiconductor layer extends in the first direction and faces side surfaces in a second direction intersecting the first direction, of the plurality of control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. In addition, the first semiconductor layer includes: a first portion having a first plane orientation; and a second portion having a second plane orientation which is different from the first plane orientation.

Abstract: The present application relates to an organic light emitting device.

Abstract: Image sensors, and electronic devices including the image sensors, include a first photoelectronic device including at least one of a blue photoelectronic device sensing light in a blue wavelength region, a red photoelectronic device sensing light in a red wavelength region, and a green photoelectronic device sensing light in a green wavelength region, and a second photoelectronic device stacked on one side of the first photoelectronic device without being interposed by a color filter, wherein the second photoelectronic device senses light in an infrared region.

Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.

Abstract: A method for sputtering an aluminum layer on a surface of a semiconductor device is presented. The method includes three sputtering steps for depositing the aluminum layer, where each sputtering step includes at least one sputtering parameter that is different from a corresponding sputtering parameter of another sputtering step. The surface of the semiconductor device includes a dielectric layer having a plurality of openings formed through the dielectric layer.

Abstract: A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.

Abstract: Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well. First and second body contacts are coupled with the first well, and the first and second body contacts each have the first conductivity type. A triggering device may be coupled with the first body contact.

Abstract: A light-emitting device includes: a light-emitting layer; a first layer located on a light-emitting side of the light-emitting layer; and a second layer located on a light-emitting side of the first layer, and in contact with the first layer. A concavo-convex structure composed of a plurality of convex portions having two or more steps is formed at a boundary between the first layer and the second layer, a refractive index of the first layer is higher than a refractive index of the second layer, and a concavo-convex pattern of the concavo-convex structure is a pattern formed by a space-filling curve or a fractal tiling pattern.

Abstract: An optical sensor package module and a manufacturing method thereof are provided. The optical sensor package module includes a substrate, a sensor chip and a shielding assembly. The sensor chip is disposed on the substrate and includes an array of pixels located at a top side thereof for receiving light. The shielding assembly surrounds the sensor chip for limiting influx of light onto the sensor chip, and the shielding assembly has a first aperture to expose at least a first subset of the pixels that is configured to receive corresponding light.

Abstract: In a general aspect, a device can include a substrate, a first pillar of a first conductivity type, a second pillar of a second conductivity type, the first pillar and the second pillar being alternately disposed, and a metal layer having a first portion disposed on the first pillar and a second portion disposed on the second pillar. The first portion of the metal layer can be wider than the second portion of the metal layer.

Abstract: An organic electroluminescent device having low driving voltage, high luminous efficiency, and a long lifetime is provided by combining various materials for an organic electroluminescent device. In the organic electroluminescent device having at least an anode, a hole injection layer, a first hole transport layer, a second hole transport layer, a light emitting layer, an electron transport layer, and a cathode in this order, the hole injection layer includes an arylamine compound of the following general formula (1) and an electron acceptor. In the formula, Ar1 to Ar4 may be the same or different, and represent a substituted or unsubstituted aromatic hydrocarbon group, a substituted or unsubstituted aromatic heterocyclic group, or a substituted or unsubstituted condensed polycyclic aromatic group.

Abstract: A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.

Abstract: A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Abstract: A semiconductor device includes a substrate having an insulating surface; a circuit including a transistor provided on the insulating surface and including a semiconductor layer, an insulating layer and a conductive layer; and a line provided on the insulating surface, the line extending in a first direction. The line includes a core containing a resin material and a conductive portion covering the core as seen in a cross-sectional view taken along a second direction crossing the first direction.

Abstract: A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.

Abstract: A semiconductor device includes a substrate comprising a WELL region, a gate electrode comprising a gate length disposed on the WELL region, and first and second drift regions which overlap with the gate electrode. The first and second draft regions may overlap with the gate electrode at an overlapping length which is a percentage of the gate length.