Abstract: A display device includes two or more transistors in one pixel, and the two or more transistors include a first transistor of which a channel semiconductor layer is polycrystalline silicon, and a second transistor of which a channel semiconductor layer is an oxide semiconductor.

Abstract: The disclosed technology relates to a metal-insulator-metal capacitor (MIMCAP) integrated as part of a back-end-of-line of an integrated circuit (IC). In one aspect, a MIMCAP comprises a first planar electrode having perforations formed therethrough, and a metal-insulator-metal (MIM) stack lining inner surfaces of cavities formed in the perforations and extending into the substrate. The MIMCAP additionally comprises a second electrode having a planar portion and metal extensions extending from the planar portion into the cavities. The first electrode and the planar portion of the second electrode are formed of or comprise planar metal areas of the respective metallization levels, which can be formed by a damascene process, which allows for a reduction of the series resistance. A low aspect ratio can be obtained using one electrode having a 3D-structure (the electrode having extensions extending into the cavities).

Abstract: A deep trench capacitor and a method for providing the same in a semiconductor process are disclosed. The method includes forming a plurality of deep trenches in a first region of a semiconductor wafer, the first region having well doping of a first type. A dielectric layer is formed on a surface of the plurality of deep trenches and a doped polysilicon layer is deposited to fill the plurality of deep trenches, with the doped polysilicon being doped with a dopant of a second type. Shallow trench isolation is formed overlying the dielectric layer at an intersection of the dielectric layer with the surface of the semiconductor wafer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure and a second fin structure disposed over the substrate. The semiconductor device structure includes a first gate stack overlapping the first fin structure. The first gate stack has a first width. The first gate stack includes a first work function layer. A first top surface of the first work function layer is positioned above the first fin structure by a first distance. The semiconductor device structure includes a second gate stack disposed overlapping the second fin structure. The first width is less than a second width of the second gate stack. A second top surface of a second work function layer of the second gate stack is positioned above the second fin structure by a second distance. The first distance is less than the second distance.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins and a source/drain structure. The semiconductor fins and the source/drain structure are located on the semiconductor substrate, and the source/drain structure is connected to the semiconductor fins. The source/drain structure has a top portion with a W-shape cross section for forming a contact landing region. The semiconductor device may further include a plurality of capping layers located on a plurality of recessed portions of the top portion.

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.

Abstract: A method for fabricating a structure having surfaces exposed to plasma in a substrate processing system includes providing a sacrificial substrate having a first shape, machining the substrate into a second shape, the second shape having dimensions corresponding to a desired final shape of the structure, depositing a layer of material on the substrate, machining first selected portions of the layer of material to expose the substrate within the layer of material, removing remaining portions of the substrate, and machining second selected portions of the layer of material into the structure having the desired final shape without machining the surfaces of the structure that are exposed to plasma during processing.

Abstract: A magnetic memory of an embodiment includes: a first nonmagnetic layer including a first and second faces; a first and second wirings disposed on a side of the first face; a third wiring disposed on a side of the second face; a first transistor, one of the source and the drain being connected to the first wiring, the other one being connected to the first nonmagnetic layer; a second transistor, one of source and drain being connected to the second wiring, the other one being connected to the first nonmagnetic layer; a magnetoresistive element disposed between the first nonmagnetic layer and the third wiring, a first terminal of the magnetoresistive element being connected to the first nonmagnetic layer; and a third transistor, one of source and drain of the third transistor being connected to the second terminal, the other one being connected to the third wiring.

Abstract: An inverted-structure light-emitting element is provided. One embodiment of the invention disclosed in this specification is a light-emitting element including a cathode, a layer serving as a buffer over the cathode, an electron-injection layer over the layer serving as a buffer, a light-emitting layer over the electron-injection layer, and an anode over the light-emitting layer. The electron-injection layer includes an alkali metal or an alkaline earth metal. The layer serving as a buffer includes an electron-transport material. In the inverted-structure light-emitting element, contact of the alkali metal or alkaline earth metal included in a material of the electron-injection layer with the already formed cathode increases the driving voltage of an EL element and reduces emission efficiency. This problem becomes prominent particularly when the cathode includes an oxide conductive film. To prevent this, the layer serving as a buffer is provided between the cathode and the electron-injection layer.

Abstract: A semiconductor device includes interlayer insulating layers and conductive patterns alternately stacked over a pipe gate, a first slit and a second slit penetrating the interlayer insulating layers and the conductive patterns and crossing each other, an etch stop pad groove overlapping an intersection of the first slit and the second slit, arranged in the pipe gate, and connected to the first slit or the second slit, and slit insulating layers filling the first slit, the second slit and the etch stop pad groove.

Abstract: An integrated circuit has a substrate, a super-capacitor supported by the substrate, and a battery supported by the substrate. The super-capacitor includes a super-capacitor electrode and a shared electrode, and the battery has a battery electrode and the prior noted shared electrode. The super-capacitor and battery form at least a part of a monolithic integrated circuit.

Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.

Abstract: According to one embodiment, a magnetic memory device includes a first insulating film provided on a semiconductor region, and having a portion located in a memory cell array area and thicker than a portion located in a peripheral circuit area, a plurality of conductive plugs located in the memory cell array area and provided in the first insulating film, stacked structures located in the memory cell array area, provided on the conductive plugs, and each having layers including a magnetic layer, and transistors located in the peripheral circuit area, and each including a gate electrode provided on the semiconductor region and covered with the first insulating film, wherein a thickness t0 from a main surface of the semiconductor region to a lower surface of each stacked structure is greater than a predetermined value.

Abstract: A light emitting device includes a semiconductor light emitting element; a mounting substrate; a support substrate; a joining layer which joins the semiconductor light emitting element and the mounting substrate together, is a sintered body of metal particles, and has a pore; and a joining layer which joins the mounting substrate and the support substrate together, is a sintered body of metal particles, and has a pore, in which a porosity of the joining layer is lower than a porosity of the joining layer.

Abstract: Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an interior of the first insulative structure, and a ferroelectric structure lines an interior of the first conductive structure. A second conductive structure is within a lower region of the ferroelectric structure, and the second conductive structure has an uppermost surface beneath an uppermost surface of the first conductive structure. A second insulative structure is over the second conductive structure and within the ferroelectric structure. A pair of source/drain regions are adjacent an upper region of the first insulative structure and are on opposing sides of the first insulative structure from one another.

Abstract: A semiconductor device according to an embodiment includes: a first GaN based semiconductor layer; a second GaN based semiconductor layer disposed on the first GaN based semiconductor layer and having a bandgap larger than that of the first GaN based semiconductor layer; a source electrode disposed on the second GaN based semiconductor layer; a drain electrode disposed on the second GaN based semiconductor layer; a p-type third GaN based semiconductor layer disposed between the source electrode and the drain electrode on the second GaN based semiconductor layer; a gate electrode disposed on the third GaN based semiconductor layer; and a p-type fourth GaN based semiconductor layer disposed between the gate electrode and the drain electrode on the second GaN based semiconductor layer and disposed separated from the third GaN based semiconductor layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate. The semiconductor device structure also includes a source/drain structure over the semiconductor substrate, and the source/drain structure includes a dopant. The semiconductor device structure further includes a channel region under the gate stack. In addition, the semiconductor device structure includes a semiconductor layer surrounding the source/drain structure. The semiconductor layer is configured to prevent the dopant from entering the channel region.

Abstract: An optoelectronic component includes a housing having a first cavity open toward an upper side of the housing, and a second cavity open toward the upper side of the housing, wherein the first cavity and the second cavity connect by a connecting channel, an optoelectronic semiconductor chip is arranged in the first cavity, a potting material is arranged in a region of the first cavity enclosing the optoelectronic semiconductor chip, a bond wire is arranged between an electrical contact surface of the optoelectronic semiconductor chip and a bond surface of the housing, and the bond surface is arranged in the connecting channel.

Abstract: An image sensor structure is provided. The image sensor device structure includes a substrate, and the substrate includes an array region and a peripheral region. The image sensor device structure includes an anti-reflection layer formed on the substrate and a buffer layer formed on the anti-reflection layer. The image sensor device structure includes a first etch stop layer formed on the buffer layer and a metal grid structure formed on the first etch stop layer. The image sensor device structure also includes a dielectric layer formed on the metal grid structure.

Abstract: An LED package structure includes a ceramic substrate, a ceramic board, a light-emitting unit, a first adhesive layer, a second adhesive layer, and a cover. The ceramic board having a thru-hole is disposed on the ceramic substrate. The light-emitting unit is disposed on the ceramic substrate and is arranged in the thru-hole of the ceramic board. The first and second adhesive layers are disposed on the ceramic board, and the second adhesive layer covers the first adhesive layer. The cover is fixed on the ceramic board by the first and second adhesive layers. Thus, the shearing force of the LED package structure of the instant disclosure is increased by having the first and second adhesive layers, which are connected to each other.