Abstract: A photoelectric conversion device comprises a photoelectric conversion layer; a plurality of structures made of a dielectric substance; and a medium layer for transmitting light interposed between the photoelectric conversion layer and the structures or between the structures, or both, wherein the plurality of structures and the medium layer satisfy ndie>nmed and Dave×nmed/?max<0.3, wherein ?max is a maximal sensitivity wavelength at which the sensitivity of the photoelectric conversion layer to light energy is maximal, nmed is a refractive index of the medium layer at the wavelength ?max, ndie is a refractive index of the structures at the wavelength ?max, and Dave is an average of shortest distances between an light exposure surface of the photoelectric conversion layer and the structures.

Abstract: In a non-volatile memory, writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film, which serves as a charge accumulation layer. The gate electrode of a memory cell has a laminated structure made of a plurality of polysilicon films with different impurity concentrations. In a two-layered structure the gate electrode has a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon. Holes are injected into the charge accumulation layer from the gate electrode.

Abstract: A solid-state imaging apparatus includes a plurality of pixels each including a photoelectric conversion unit and pixel transistors, which are formed on a semiconductor substrate; a floating diffusion unit in the pixel; a first-conductivity-type ion implantation area for surface pinning, which is formed over the surface on the side of the photoelectric conversion unit and the surface of the semiconductor substrate; and a second-conductivity-type ion implantation area for forming an overflow path serving as an overflow path for the floating diffusion unit, the second-conductivity-type ion implantation area being formed below the entire area of the first-conductivity-type ion implantation area. An overflow barrier is formed using the second-conductivity-type ion implantation area. A charge storage area is formed using an area in which the second-conductivity-type semiconductor area and the second-conductivity-type ion implantation area superpose each other.

Abstract: With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

Abstract: System-in packages, or multichip modules, are described which can include multi-layer chips and multi-layer dummy substrates over a carrier, multiple through vias blindly or completely through the multi-layer chips and completely through the multi-layer dummy substrates, multiple metal plugs in the through vias, and multiple metal interconnects, connected to the metal plugs, between the multi-layer chips. The multi-layer chips can be connected to each other or to an external circuit or structure, such as mother board, ball grid array (BGA) substrate, printed circuit board, metal substrate, glass substrate, or ceramic substrate, through the metal plugs and the metal interconnects.

Abstract: Photolithographic methods of forming a roughened surface for an LED to improve LED light emission efficiency are disclosed. The methods include photolithographically imaging a phase-shift mask pattern onto a photoresist layer of a substrate to form therein a periodic array of photoresist features. The roughened substrate surface is created by processing the exposed photoresist layer to form a periodic array of substrate posts in the substrate surface. A p-n junction multilayer structure is then formed atop the roughened substrate surface to form the LED. The periodic array of substrate posts serve as scatter sites that improve the LED light emission efficiency as compared to the LED having no roughened substrate surface. The use of the phase-shift mask enables the use of affordable photolithographic imaging at a depth of focus suitable for non-flat LED substrates while also providing the needed resolution to form the substrate posts.

Abstract: A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments.

Abstract: A method for producing a plurality of radiation-emitting components includes A) providing a carrier layer having a plurality of mounting regions separated from one another by separating regions; B) applying an interlayer to the separating regions; C) applying a respective radiation-emitting device to each of the plurality of mounting regions; D) applying a continuous potting layer to the radiation-emitting device and the separating regions; E) severing the potting layer and partially severing the interlayer in the separating regions of the carrier layer in a first separating step; and F) partially severing the interlayer and severing the carrier layer in a second separating step, wherein the interlayer is completely severed by the first and the second separating step.

Abstract: An optoelectronic component (1) is specified, comprising a connection carrier (2) on which a radiation-emitting semiconductor chip (3) is arranged, and a conversion element (4) fixed to the connection carrier (2). The conversion element (4) spans the semiconductor chip (3) in such a way that the semiconductor chip (3) is surrounded by the conversion element (4) and the connection carrier (2), and the conversion element (4) consists of one of the following materials: ceramic, glass ceramic.

Abstract: A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential.

Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Abstract: A method and circuit in which the drive strength of a FinFET transistor can be selectively modified, and in particular can be selectively reduced, by omitting the LDD extension formation in the source and/or in the drain of the FinFET. One application of this approach is to enable differentiation of the drive strengths of transistors in an integrated circuit by applying the technique to some, but not all, of the transistors in the integrated circuit. In particular in a SRAM cell formed from FinFET transistors the application of the technique to the pass-gate transistors, which leads to a reduction of the drive strength of the pass-gate transistors relative to the drive strength of the pull-up and pull-down transistors, results in improved SRAM cell performance.

Abstract: To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an Lov region is provided.

Abstract: A light-emitting diode (LED) with a mirror protection layer includes sequentially stacked an N-type electrode, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a metal mirror layer, a protection layer, a buffer layer, a binding layer, a permanent substrate, and a P-type electrode. The protection layer is made of metal oxide, and has a hollow frame for covering or supporting edges of the metal mirror layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, wherein an amorphous semiconductor film comprising a microcrystal is annealed using a microwave, to crystallize the amorphous semiconductor film comprising the microcrystal using the microcrystal as a nucleus.

Abstract: Integrated circuit devices include thermal image sensors that utilize quantum dots therein to provide negative resistance characteristics to at least portions of the sensors. The thermal image sensor may include a sensing unit configured to absorb radiation incident on a first surface thereof and first and second electrodes electrically coupled to the sensing unit. The sensing unit includes a plurality of quantum dots therein, which may extend between the first and second electrodes. These quantum dots may be configured to impart a negative resistance characteristic to the sensing unit. In particular, the sensing unit may include a sensing layer having first and second opposing ends, which are electrically coupled to the first and second electrodes, respectively, and the plurality of quantum dots may be distributed within the sensing layer.

Abstract: A semiconductor wafer including an electrostatic discharge (ESD) protective device, and methods for fabricating the same. In one aspect, the method includes forming a first semiconductor device in a first semiconductor die region on the semiconductor wafer; forming a second semiconductor device in a second semiconductor die region on the semiconductor wafer; and forming a protective device in a scribe line region between (i) the first semiconductor die region and (ii) the second semiconductor die region.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor device body and an insulating adhesive layer. The semiconductor device body is formed with a square plate shape and has an element portion provided on a first major surface. The insulating adhesive layer is provided to cover a second major surface of the semiconductor device body and one or two of four side faces of the semiconductor device body.

Abstract: A semiconductor device including: a bit line being arranged on top surfaces of first and second contact plugs via a first insulation layer and extending in a direction connecting a first impurity diffusion layer and a second impurity diffusion layer; a bit line contact plug being formed through the first insulation layer and electrically connecting the bit line to the first contact plug; a first cell capacitor having a first lower electrode beside one of side surfaces of the bit line; a first insulation film insulating the bit line and the first lower electrode from each other; and a first contact conductor electrically connecting a bottom end of the first lower electrode to a side surface of the second contact plug.

Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.