Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: A device and method of fabricating the same are disclosed. In an example, a device includes a first fin Field Effect Transistors (finFET) formed on a substrate. The first finFET including a fin formed on the substrate. The device further includes a second finFET formed on the substrate. The first finFET and the second finFET share the fin and wherein the first finFET is without any low density doped (LDD) extension region in the substrate and wherein the second FinFET is associated with a first LDD extension region formed in the substrate such that a drive strength of the second finFET is greater relative to a drive strength of the first finFET.

Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.

Abstract: According to one embodiment, an information recording device includes first and second electrodes, a variable resistance layer between the first and second electrodes, and a control circuit which controls the variable resistance layer to n (n is a natural number except 1) kinds of resistance. The variable resistance layer comprises a material filled between the first and second electrodes, and particles arranged in a first direction from the first electrode to the second electrode in the material, and each of the particles has a resistance lower than that of the material. A resistance of the variable resistance layer is decided by a short between the first electrode and at least one of the particles.

Abstract: An electronic device comprises at least one static induction transistor (14; 114; 214) and at least one thin film transistor (16; 116). The static induction transistor (14; 114; 214) has a first channel (14.4; 114.4; 214.4) of a semi conducting material extending between a first main electrode (14.2; 114.2; 214.2) and a second main electrode (14.3; 114.3) through a first and a second insulating layer (11, 13; 111, 113), and has a first control electrode (14.1; 114.1) surrounding the first channel and extending between the first and the second insulating layer. The thin film transistor (16; 116) has a third main electrode (16.2; 116.2) and a fourth main electrode (16.3; 116.3) coupled by a second channel (16.4; 116.4) of a semi conducting material and a second control electrode (16.1; 116.1). At least one of the first and the second insulating layer functions as a dielectric layer between the second control electrode and the second channel.

Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.

Abstract: A semiconductor structure includes a temporary substrate; a first semiconductor layer positioned on the temporary substrate; a dielectric layer comprising a plurality of patterned nano-scaled protrusions disposed on the first semiconductor layer; a dielectric layer surrounding the plurality of patterned nano-scaled protrusions and disposed on the first semiconductor layer; and a second semiconductor layer positioned on the dielectric layer, wherein the top surfaces of the patterned nano-scaled protrusions are in contact with the bottom of the second semiconductor layer. An etching process is performed on the semiconductor structure to separate the first semiconductor layer and the second semiconductor layer, in order to detach the temporary substrate from the second semiconductor layer and transfer the second semiconductor layer to a permanent substrate.

Abstract: In a gallium nitride based compound semiconductor light-emitting element including an active layer, the active layer includes a well layer 104 and a barrier layer 103, each of which is a semiconductor layer of which the growing plane is an m plane. The well layer 104 has a lower surface and an upper surface and has an In composition distribution in which the composition of In changes according to a distance from the lower surface in a thickness direction of the well layer 104. The In composition of the well layer 104 becomes a local minimum at a level that is defined by a certain distance from the lower surface and that portion of the well layer 104 where the In composition becomes the local minimum runs parallel to the lower surface.

Abstract: A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential.

Abstract: According to one embodiment, there is disclosed a MEMS element. The MEMS element includes a lower electrode having a surface on which a plurality of minute convex portions are formed. A plurality of dielectric bumps are provided on the upper surface of the lower electrode and are thicker than heights of the convex portions. A dielectric layer is provided on the dielectric bumps and the lower electrode. An upper electrode is provided above the dielectric layer. The upper electrode is movable so as to vary capacitance between the upper electrode and the lower electrode.

Abstract: Disclosed herein is a device that includes: external terminals; a first chip including a first control circuit that generates a first control signal; and a second chip stacked with the first chip. The second chip includes: a first test terminal supplied with a first test signal and being free from connecting to any one of the external terminals; a second test terminal supplied with the first test signal and coupled to one of the external terminals without connecting to any one of control circuits of the first chip; a first normal terminal supplied with the first control signal and coupled to another of the external terminals with an intervention of the first control circuit of the first chip; and a first selection circuit including first input node coupled in common to the first and second test terminals and the second input node coupled to the first normal terminal.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a conductive member, a semiconductor pillar, and a charge storage layer. The stacked body is provided above the substrate. The stacked body includes a plurality of insulating films stacked alternately with a plurality of electrode films. A plurality of terraces are formed in a stairstep configuration along only a first direction in an end portion of the stacked body on the first-direction side. The first direction is parallel to an upper face of the substrate. The plurality of terraces are configured with upper faces of the electrode films respectively. The conductive member is electrically connected to the terrace to connect electrically the electrode film to the substrate by leading out the electrode film in a second direction parallel to the upper face of the substrate and orthogonal to the first direction.

Abstract: Lighting devices including light-emitting diodes and associated devices, systems, and methods are disclosed herein. A lighting device configured in accordance with a particular embodiment includes a lighting-emitting diode and an optical component along a radiation path of the lighting-emitting diode. The optical component includes a color-converting material with walls defining a pattern, the walls extending generally entirely through a thickness of the color-converting material. A total surface area of the walls within a primary zone of the optical component is greater than a total surface area of color-converting features at a major side of the color-converting material. A method for making a lighting device in accordance with a particular embodiment includes combining an optical component and a light-emitting diode, and shaping a color-converting material of the optical component to have a thickness and a pattern of walls selected to control the color of light output from the lighting device.

Abstract: A light emitting device package may be provided that includes: a package body which includes a first cavity and a second cavity which are formed to be depressed in at least a portion of the package body; a first light emitting device and a second light emitting device, each of which is disposed in the first cavity and the second cavity respectively; and a first fluorescent substance and a second fluorescent substance, each of which is filled in the first cavity and the second cavity respectively.

Abstract: A lighting device includes an electrically activated emitter, a first layer that contains a first encapsulant material, and a second layer that contains a second encapsulant material, with a textured interface between the first layer and the second layer. Additional layers including further encapsulant materials and/or lumiphoric materials may be provided. Multiple textured interfaces may be provided. Textured interfaces may be arranged as lenses, including Fresnel lenses.

Abstract: The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method.

Abstract: According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided at the intersection of the first interconnect line and the second interconnect line and which includes a memory element and a non-ohmic element that are connected in series. The memory element stores data in accordance with a change in a resistance state. The non-ohmic element includes a metal layer, a first semiconductor layer containing a first impurity, and a second semiconductor layer which is provided between the first semiconductor layer and the metal layer and which has an unevenly distributed layer.

Abstract: An organic electroluminescence device includes a first electrode, a second electrode located on a light extraction side and having a metal film, and an organic compound layer provided between the first electrode and the second electrode and including an emission layer. In addition, a first inorganic protective layer is in direct contact with the second electrode and has a specified thickness.

Abstract: A light emitting device includes a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and a light extraction structure that extracts light from the light emitting structure. The light extraction structure includes at least a first light extraction zone and a second light extraction zone, where a period and/or size of first concave and/or convex structures of the first light extraction zone is different from a period and/or size of second concave and/or convex structures of the second light extraction zone.