Patents Examined by David Yi
  • Patent number: 11954356
    Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Qiuxu Zhuo, Anthony Luck
  • Patent number: 11954493
    Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Steven Jeffrey Wallach
  • Patent number: 11947837
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11941287
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, a Write-Same operation from a host for a range of logical block addresses of a destination. Data may be recorded in a buffer to indicate that the Write-Same operation is complete prior to completing the Write-Same operation. An acknowledgment may be sent to the host that the Write-Same operation is complete prior to flushing to a final destination. The Write-Same operation for the logical block addresses of the destination may be performed after sending the acknowledgment to the host that the Write-Same operation is complete.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: March 26, 2024
    Assignee: EMC IP Holding Company, LLC
    Inventors: Bar David, Ronen Gazit
  • Patent number: 11934275
    Abstract: A synthetic full backup of a source volume representing a state of the volume at a current time is retrieved, the synthetic full having been generated by merging a full backup of the volume performed at an initial time with an incremental backup of the volume performed at the current time, after the initial time. A bitmap tracking changes to the volume made between the initial and current times is accessed. The bitmap is used to identify a location on the volume having changes made between the initial and current times. First data written to the location on the volume is read. Second data written to the same location on the synthetic full backup is read. First and second checksums are generated based on the first and second data, respectively. The checksums are compared and if any do not match, an indication is generated that the synthetic full is corrupt.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 19, 2024
    Assignee: Dell Products L.P.
    Inventors: Sunil Yadav, Shelesh Chopra
  • Patent number: 11934682
    Abstract: A technological approach to management of data lifecycle includes protecting data. Datasets from distinct computing environments of an organization can be scanned to identify data elements subject to protection, such as sensitive data. Data lineage associated with the identified data elements can be determined including relationships amongst other data and linkages between computing environments or systems. The identified elements can be automatically protected based at least in part on the lineage such as by masking, encryption, or tokenization. Further, the datasets can be monitored to create audit trails for interactions with the datasets.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: March 19, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Kaushik Kishanlal Bhatt, Swapnil Sharma
  • Patent number: 11934672
    Abstract: A computer-implemented method and a computer system for improving cached workload management. A host, which is in a system comprising the host and a storage system, obtains information about classes of applications accessing the storage system. The host determines input/output queues dedicated to respective ones of the classes. The storage system creates, in the storage system, cache partitions dedicated to the respective ones of the classes, based on information about classes. The host creates the input/output queues and sets bit flags for respective ones of the input/output queues. The host pumps inputs/outputs coming from the respective ones of the classes to the respective ones of the input/output queues. The storage system directs the input/output queues to respective ones of the cache partitions.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: March 19, 2024
    Assignee: International Business Machines Corporation
    Inventors: Kushal S. Patel, Ankur Srivastava, Subhojit Roy, Sarvesh S. Patel
  • Patent number: 11928345
    Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: March 12, 2024
    Assignee: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Jin Dai, Yunsen Zhang
  • Patent number: 11922199
    Abstract: An in-guest agent in a virtual machine (VM) operates in conjunction with a replication module. The replication module performs continuous data protection (CDP) by saving images of the VM as checkpoints at a disaster recovery site over time. Concurrently, the in-guest agent monitors for behavior in the VM that may be indicative of the presence of malicious code. If the in-guest agent identifies behavior (at a particular point in time) at the VM that may be indicative of the presence of malicious code, the replication module can tag a checkpoint that corresponds to the same particular point in time as a security risk. One or more checkpoints generated prior to the particular time may be determined to be secure checkpoints that are usable for restoration of the VM.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: March 5, 2024
    Assignee: VMware, Inc.
    Inventors: Sunil Hasbe, Shirish Vijayvargiya
  • Patent number: 11921589
    Abstract: Any point in time backups for distributed consistency is disclosed. IOs from a consistency group are received by multiple aggregators and stored in corresponding journals. In response to a bookmark, the multiple journals are synthesized to create a do stream or to add the multiple journals to the do stream. A full synchronization operation can be performed simultaneously with replication operations.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 5, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jehuda Shemer, Valerie Lotosh, Saar Cohen, Erez Sharvit
  • Patent number: 11914530
    Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: February 27, 2024
    Inventors: Robert M. Walker, Dan Skinner, Todd A. Merritt, J. Thomas Pawlowski
  • Patent number: 11915022
    Abstract: Mechanisms for reducing memory inconsistencies between two synchronized computing devices are provided. A first hypervisor module of a first computing device iteratively determines that content of a memory page of a plurality of memory pages has been modified. The content of the memory page is sent to a second hypervisor module on a second computing device. At least one other memory page of the plurality of memory pages is identified, and a verification value based on the content of the at least one other memory page is generated. The verification value and a memory page identifier that identifies the at least one other memory page is sent to the second hypervisor module on the second computing device.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: February 27, 2024
    Assignee: Red Hat, Inc.
    Inventor: David A. Gilbert
  • Patent number: 11914889
    Abstract: A current cycle count associated with a memory sub-system is determined. The current cycle count is compared to a set of cycle count threshold levels to determine a current lifecycle stage of the memory sub-system. A temperature associated with the memory sub-system is measured. The temperature is compared to a set of temperature levels to determine a current temperature level of the memory sub-system. A write-to-read delay time corresponding to the current lifecycle stage and the current temperature level is determined.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Tingjun Xie, Wei Wang, Frederick Adi, Zhenming Zhou, Jiangli Zhu
  • Patent number: 11914892
    Abstract: A storage device includes a non-volatile memory including memory blocks, and a storage controller including a history buffer including plural history read level storage areas corresponding to the memory blocks. The storage controller dynamically adjusts a number of the history read level storage areas allocated to one or more of the plurality of memory blocks based on reliabilities of the memory blocks during runtime of the storage device. The storage controller increases a number of history read level storage areas allocated to a first memory block among the memory blocks that has a relatively low reliability with respect to the reliabilities of remaining ones of the memory blocks.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwangwoo Lee, Sangjin Yoo, Yeonji Kim, Jeongkeun Park, Jeongwoo Lee
  • Patent number: 11914866
    Abstract: One example method includes performing delta operations to protect data. During a delta operation, a primary map and a secondary map are processed using bit logic. The bit logic determines how to handle data stored at a location on the volume associated with an entry in the primary map and included in the current delta operation when a new write for the same location is received as the corresponding entry in the primary map is processed.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: February 27, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Jehuda Shemer, Ravi Vijayakumar Chitloor
  • Patent number: 11907569
    Abstract: A host stores “context” metadata for logical block addresses (LBAs) in a manner tied to physical location. Notwithstanding log-structured or copy on write processes, the host is then provided with immediate context when the host is called upon to assist a memory controller with data identified by physical location, for example, for memory reconfiguration, garbage collection, wear leveling or other processes. The metadata for example can provide the host with insight as to which data may be moved to enhance performance optimization and where that data can be placed. In one embodiment, the host writes back one or more references that span multiple layers of indirection in concert with write of the underlying data; in another embodiment, the context can point to other metadata.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: February 20, 2024
    Assignee: Radian Memory Systems, Inc.
    Inventors: Alan Chen, Craig Robertson, Robert Lercari, Andrey V. Kuzmin
  • Patent number: 11907076
    Abstract: The present disclosure relates to a data snapshot method and apparatus, a computer device and a storage medium. The method includes: acquiring the capacity of to-be-written data after snapshot, and comparing the capacity of the to-be-written data with a preset capacity; when the capacity of the to-be-written data is greater than or equal to the preset capacity, writing the to-be-written data into a snapshot volume in a Redirect On Write manner; when the capacity of the to-be-written data is less than the preset capacity, writing the to-be-written data into a solid state drive in a Redirect On Write manner; and when a background write-back thread detects that there is data writing into the solid state drive, writing corresponding data in a source volume into the snapshot volume in a Copy On Write manner, and writing the to-be-written data in the solid state drive into the source volume.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: February 20, 2024
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Bin Hou
  • Patent number: 11899980
    Abstract: An operation method of a UFS device including: determining, by a host, area information for write data, wherein in a turbo read the write data is stored in a non-pinned or pinned buffer area and in a normal read the write data is stored in a user storage; transferring, by the host, a first command UFS protocol information unit (UPIU); transferring, by the UFS device, an RTT UPIU to the host, transferring, by the host, a DATA OUT UPIU to the UFS device; mapping, by UFS device, a first logical block address with a physical address of an area corresponding to the area information; transferring, by the host, a second command UPIU; and performing the turbo read on the area to read data corresponding to the first logical block address when the area corresponding to the area information is the pinned or non-pinned turbo write buffer.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunsoo Cho, Dong-Min Kim, Kyoung Back Lee
  • Patent number: 11899984
    Abstract: A message that includes a queue identifier (ID) is received from a first hardware functional module. A virtual queue is selected from a plurality of virtual queues in a shared queue structure based at least in part on the queue ID and configurable message handling settings(s). The message is stored in the selected virtual queue and a message recipient is selected from a plurality of potential message recipients based at least in part on the configurable message handling setting(s), where the plurality of potential message recipients includes the second hardware functional module and the processor module. The message is provided to the selected message recipient.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: February 13, 2024
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Zhikai Chen, Lyle E. Adams
  • Patent number: 11899957
    Abstract: Data protection operations including replication operations are disclosed. Virtual machines, applications, and/or application data are replicated according to at least one strategy. The replication strategy can improve performance of the recovery operation.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: February 13, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Bing Liu, Jehuda Shemer, Kfir Wolfson, Jawad Said